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add a bunch more evil lowering code to work around various :subreg32 modifiers
in the .td files. This gets us down to 18 failures in codegen/x86 with the new asmprinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81198 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,12 +50,12 @@ static void lower_subreg32(MCInst *MI, unsigned OpNo) {
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static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
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// Convert registers in the addr mode according to subreg64.
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for (unsigned i = 0; i != 4; ++i) {
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if (!MI->getOperand(i).isReg()) continue;
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if (!MI->getOperand(OpNo+i).isReg()) continue;
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unsigned Reg = MI->getOperand(i).getReg();
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unsigned Reg = MI->getOperand(OpNo+i).getReg();
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if (Reg == 0) continue;
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MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
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MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
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}
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}
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@ -321,6 +321,42 @@ printInstructionThroughMCStreamer(const MachineInstr *MI) {
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TmpInst.setOpcode(X86::MOVZX32rm8);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVSX16rr8:
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TmpInst.setOpcode(X86::MOVSX32rr8);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVSX16rm8:
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TmpInst.setOpcode(X86::MOVSX32rm8);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVZX64rr32:
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TmpInst.setOpcode(X86::MOV32rr);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVZX64rm32:
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TmpInst.setOpcode(X86::MOV32rm);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOV64ri64i32:
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TmpInst.setOpcode(X86::MOV32ri);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVZX64rr8:
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TmpInst.setOpcode(X86::MOVZX32rr8);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVZX64rm8:
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TmpInst.setOpcode(X86::MOVZX32rm8);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVZX64rr16:
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TmpInst.setOpcode(X86::MOVZX32rr16);
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lower_subreg32(&TmpInst, 0);
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break;
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case X86::MOVZX64rm16:
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TmpInst.setOpcode(X86::MOVZX32rm16);
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lower_subreg32(&TmpInst, 0);
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break;
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}
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printInstruction(&TmpInst);
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