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Add predicate and 's' bit operands to PICADD instruction lowering.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-14 21:28:17 +00:00
parent 3b8b2ca3a8
commit 5b46d62c44
1 changed files with 5 additions and 0 deletions
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5
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -1349,6 +1349,11 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
// Add predicate operands.
AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
// Add 's' bit operand (always reg0 for this)
AddInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(AddInst);
return;
}