The LLVM IR does not define any way to start parallel threads of execution +or to register signal handlers. Nonetheless, there are platform-specific +ways to create them, and we define LLVM IR's behavior in their presence. This +model is inspired by the C++0x memory model.
+ +We define a happens-before partial order as the least partial order +that
+Note that program order does not introduce happens-before edges +between a thread and signals executing inside that thread.
+ +Every (defined) read operation (load instructions, memcpy, atomic +loads/read-modify-writes, etc.) R reads a series of bytes written by +(defined) write operations (store instructions, atomic +stores/read-modify-writes, memcpy, etc.). For each byte, R reads the +value written by some write that it may see, given any relevant +happens-before constraints. Rbyte may +see any write to the same byte, except:
+ +Given that definition, Rbyte is defined as follows: +
R returns the value composed of the series of bytes it read. +This implies that some bytes within the value may be undef +without the entire value being undef. Note that this only +defines the semantics of the operation; it doesn't mean that targets will +emit more than one instruction to read the series of bytes.
+ +Note that in cases where none of the atomic intrinsics are used, this model +places only one restriction on IR transformations on top of what is required +for single-threaded execution: introducing a store to a byte which might not +otherwise be stored to can introduce undefined behavior.
+ + + +