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[Hexagon] Adding word loads.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-23 18:06:56 +00:00
parent c9092d2829
commit 5b7d5db23b
8 changed files with 52 additions and 48 deletions
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8
lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
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@ -141,7 +141,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
"Not a Frame Pointer, Nor a Spill Slot"); "Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset"); assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm(); int Offset = MI->getOperand(2).getImm();
if (!TII->isValidOffset(Hexagon::LDriw, Offset)) { if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) { if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
BuildMI(*MBB, MII, MI->getDebugLoc(), BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::CONST32_Int_Real), TII->get(Hexagon::CONST32_Int_Real),
@ -150,7 +150,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
HEXAGON_RESERVED_REG_1) HEXAGON_RESERVED_REG_1)
.addReg(FP) .addReg(FP)
.addReg(HEXAGON_RESERVED_REG_1); .addReg(HEXAGON_RESERVED_REG_1);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2) HEXAGON_RESERVED_REG_2)
.addReg(HEXAGON_RESERVED_REG_1) .addReg(HEXAGON_RESERVED_REG_1)
.addImm(0); .addImm(0);
@ -159,7 +159,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
} else { } else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2) HEXAGON_RESERVED_REG_2)
.addReg(HEXAGON_RESERVED_REG_1) .addReg(HEXAGON_RESERVED_REG_1)
.addImm(0); .addImm(0);
@ -167,7 +167,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
DstReg).addReg(HEXAGON_RESERVED_REG_2); DstReg).addReg(HEXAGON_RESERVED_REG_2);
} }
} else { } else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset); HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp), BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2); DstReg).addReg(HEXAGON_RESERVED_REG_2);

12
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -405,7 +405,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
TargAddr); TargAddr);
// Figure out base + offset opcode // Figure out base + offset opcode
if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed; if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io; else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io; else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
else llvm_unreachable("unknown memory type"); else llvm_unreachable("unknown memory type");
@ -602,7 +602,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = Hexagon::POST_LDriw; Opcode = Hexagon::POST_LDriw;
else else
Opcode = Hexagon::LDriw; Opcode = Hexagon::L2_loadri_io;
} else if (LoadedVT == MVT::i16) { } else if (LoadedVT == MVT::i16) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih; Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
@ -865,7 +865,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other, MVT::Other,
LD->getBasePtr(), TargetConst0, LD->getBasePtr(), TargetConst0,
Chain), 0); Chain), 0);
@ -891,7 +891,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other, MVT::Other,
LD->getBasePtr(), TargetConst0, LD->getBasePtr(), TargetConst0,
Chain), 0); Chain), 0);
@ -1045,7 +1045,7 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other, MVT::Other,
LD->getBasePtr(), LD->getBasePtr(),
TargetConst0, Chain), 0); TargetConst0, Chain), 0);
@ -1070,7 +1070,7 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
MVT::Other, MVT::Other,
LD->getBasePtr(), LD->getBasePtr(),
TargetConst0, Chain), 0); TargetConst0, Chain), 0);

16
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -78,7 +78,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: break; default: break;
case Hexagon::LDriw: case Hexagon::L2_loadri_io:
case Hexagon::LDrid: case Hexagon::LDrid:
case Hexagon::L2_loadrh_io: case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadrb_io: case Hexagon::L2_loadrb_io:
@ -533,7 +533,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MFI.getObjectSize(FI), MFI.getObjectSize(FI),
Align); Align);
if (RC == &Hexagon::IntRegsRegClass) { if (RC == &Hexagon::IntRegsRegClass) {
BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO); .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} else if (RC == &Hexagon::DoubleRegsRegClass) { } else if (RC == &Hexagon::DoubleRegsRegClass) {
BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
@ -674,8 +674,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::LDrid_indexed: case Hexagon::LDrid_indexed:
return isShiftedUInt<6,3>(MI->getOperand(2).getImm()); return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
case Hexagon::LDriw: case Hexagon::L2_loadri_io:
case Hexagon::LDriw_indexed:
return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
case Hexagon::L2_loadrh_io: case Hexagon::L2_loadrh_io:
@ -1103,8 +1102,7 @@ isValidOffset(const int Opcode, const int Offset) const {
switch(Opcode) { switch(Opcode) {
case Hexagon::LDriw: case Hexagon::L2_loadri_io:
case Hexagon::LDriw_indexed:
case Hexagon::LDriw_f: case Hexagon::LDriw_f:
case Hexagon::STriw_indexed: case Hexagon::STriw_indexed:
case Hexagon::STriw: case Hexagon::STriw:
@ -1352,10 +1350,8 @@ isConditionalLoad (const MachineInstr* MI) const {
case Hexagon::LDrid_cNotPt : case Hexagon::LDrid_cNotPt :
case Hexagon::LDrid_indexed_cPt : case Hexagon::LDrid_indexed_cPt :
case Hexagon::LDrid_indexed_cNotPt : case Hexagon::LDrid_indexed_cNotPt :
case Hexagon::LDriw_cPt : case Hexagon::L2_ploadrit_io:
case Hexagon::LDriw_cNotPt : case Hexagon::L2_ploadrif_io:
case Hexagon::LDriw_indexed_cPt :
case Hexagon::LDriw_indexed_cNotPt :
case Hexagon::L2_ploadrht_io: case Hexagon::L2_ploadrht_io:
case Hexagon::L2_ploadrhf_io: case Hexagon::L2_ploadrhf_io:
case Hexagon::L2_ploadrbt_io: case Hexagon::L2_ploadrbt_io:

38
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -1552,6 +1552,9 @@ let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>; defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
} }
let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
/// ///
// Load -- MEMri operand // Load -- MEMri operand
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC, multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
@ -1592,9 +1595,6 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
} }
let addrMode = BaseImmOffset, isMEMri = "true" in { let addrMode = BaseImmOffset, isMEMri = "true" in {
let accessSize = WordAccess in
defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;
let accessSize = DoubleWordAccess in let accessSize = DoubleWordAccess in
defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel; defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
} }
@ -1612,7 +1612,7 @@ def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
(L2_loadruh_io AddrFI:$addr, 0) >; (L2_loadruh_io AddrFI:$addr, 0) >;
def : Pat < (i32 (load ADDRriS11_2:$addr)), def : Pat < (i32 (load ADDRriS11_2:$addr)),
(LDriw ADDRriS11_2:$addr) >; (L2_loadri_io AddrFI:$addr, 0) >;
def : Pat < (i64 (load ADDRriS11_3:$addr)), def : Pat < (i64 (load ADDRriS11_3:$addr)),
(LDrid ADDRriS11_3:$addr) >; (LDrid ADDRriS11_3:$addr) >;
@ -1659,10 +1659,6 @@ multiclass LD_Idxd2<string mnemonic, string CextOp, RegisterClass RC,
} }
let addrMode = BaseImmOffset in { let addrMode = BaseImmOffset in {
let accessSize = WordAccess in
defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
13, 8>, AddrModeRel;
let accessSize = DoubleWordAccess in let accessSize = DoubleWordAccess in
defm LDrid_indexed: LD_Idxd2 <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, defm LDrid_indexed: LD_Idxd2 <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
14, 9>, AddrModeRel; 14, 9>, AddrModeRel;
@ -1682,7 +1678,7 @@ def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
(L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >; (L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))), def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
(LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >; (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset) >;
def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))), def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
(LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >; (LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
@ -3661,10 +3657,10 @@ def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
(i32 (L2_loadruh_io (i32 IntRegs:$src1), s11_1ImmPred:$offset))>; (i32 (L2_loadruh_io (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
def : Pat<(atomic_load_32 ADDRriS11_2:$src1), def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
(i32 (LDriw ADDRriS11_2:$src1))>; (i32 (L2_loadri_io AddrFI:$src1, 0))>;
def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)), def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
(i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>; (i32 (L2_loadri_io (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;
// 64 bit atomic load // 64 bit atomic load
def : Pat<(atomic_load_64 ADDRriS11_3:$src1), def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
@ -4028,7 +4024,7 @@ def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
// Convert sign-extended load back to load and sign extend. // Convert sign-extended load back to load and sign extend.
// i32 -> i64 // i32 -> i64
def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)), def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
(i64 (A2_sxtw (LDriw ADDRriS11_2:$src1)))>; (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
// Zero extends. // Zero extends.
@ -4084,18 +4080,18 @@ def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
// i32 -> i64 // i32 -> i64
def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)), def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
(i64 (A2_combinew (A2_tfrsi 0), (LDriw ADDRriS11_2:$src1)))>, (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
Requires<[NoV4T]>; Requires<[NoV4T]>;
let AddedComplexity = 100 in let AddedComplexity = 100 in
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
(i64 (A2_combinew (A2_tfrsi 0), (LDriw_indexed IntRegs:$src1, (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
s11_2ExtPred:$offset)))>, s11_2ExtPred:$offset)))>,
Requires<[NoV4T]>; Requires<[NoV4T]>;
let AddedComplexity = 10 in let AddedComplexity = 10 in
def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)), def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
(i32 (LDriw ADDRriS11_0:$src1))>; (i32 (L2_loadri_io AddrFI:$src1, 0))>;
// Map from Rs = Pd to Pd = mux(Pd, #1, #0) // Map from Rs = Pd to Pd = mux(Pd, #1, #0)
def : Pat <(i32 (zext (i1 PredRegs:$src1))), def : Pat <(i32 (zext (i1 PredRegs:$src1))),
@ -4116,14 +4112,14 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i64 (zextloadi32 (i32 (add IntRegs:$src2, (i64 (zextloadi32 (i32 (add IntRegs:$src2,
s11_2ExtPred:$offset2)))))), s11_2ExtPred:$offset2)))))),
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(LDriw_indexed IntRegs:$src2, (L2_loadri_io IntRegs:$src2,
s11_2ExtPred:$offset2)))>; s11_2ExtPred:$offset2)))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))), (i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$srcLow)))), (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(LDriw ADDRriS11_2:$srcLow)))>; (L2_loadri_io AddrFI:$srcLow, 0)))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))), (i32 32))),
@ -4137,14 +4133,14 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i64 (zextloadi32 (i32 (add IntRegs:$src2, (i64 (zextloadi32 (i32 (add IntRegs:$src2,
s11_2ExtPred:$offset2)))))), s11_2ExtPred:$offset2)))))),
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(LDriw_indexed IntRegs:$src2, (L2_loadri_io IntRegs:$src2,
s11_2ExtPred:$offset2)))>; s11_2ExtPred:$offset2)))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))), (i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$srcLow)))), (i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg), (i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(LDriw ADDRriS11_2:$srcLow)))>; (L2_loadri_io AddrFI:$srcLow, 0)))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh), def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))), (i32 32))),
@ -4155,7 +4151,7 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
// Any extended 64-bit load. // Any extended 64-bit load.
// anyext i32 -> i64 // anyext i32 -> i64
def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)), def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
(i64 (A2_combinew (A2_tfrsi 0), (LDriw ADDRriS11_2:$src1)))>, (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,
Requires<[NoV4T]>; Requires<[NoV4T]>;
// When there is an offset we should prefer the pattern below over the pattern above. // When there is an offset we should prefer the pattern below over the pattern above.
@ -4170,7 +4166,7 @@ def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
// ******************************************** // ********************************************
let AddedComplexity = 100 in let AddedComplexity = 100 in
def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
(i64 (A2_combinew (A2_tfrsi 0), (LDriw_indexed IntRegs:$src1, (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,
s11_2ExtPred:$offset)))>, s11_2ExtPred:$offset)))>,
Requires<[NoV4T]>; Requires<[NoV4T]>;

8
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -460,23 +460,23 @@ def: Pat <(i64 (extloadi16 (add (i32 IntRegs:$src1),
// zext i32->i64 // zext i32->i64
def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)), def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
(i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>, (i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;
let AddedComplexity = 100 in let AddedComplexity = 100 in
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
(i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1, (i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1,
s11_2ExtPred:$offset)))>, s11_2ExtPred:$offset)))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;
// anyext i32->i64 // anyext i32->i64
def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)), def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
(i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>, (i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;
let AddedComplexity = 100 in let AddedComplexity = 100 in
def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))), def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
(i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1, (i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1,
s11_2ExtPred:$offset)))>, s11_2ExtPred:$offset)))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;

2
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -159,7 +159,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// //
// r0 = add(r30, #10000) // r0 = add(r30, #10000)
// r0 = memw(r0) // r0 = memw(r0)
if ( (MI.getOpcode() == Hexagon::LDriw) || if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||
(MI.getOpcode() == Hexagon::LDrid) || (MI.getOpcode() == Hexagon::LDrid) ||
(MI.getOpcode() == Hexagon::L2_loadrh_io) || (MI.getOpcode() == Hexagon::L2_loadrh_io) ||
(MI.getOpcode() == Hexagon::L2_loadruh_io) || (MI.getOpcode() == Hexagon::L2_loadruh_io) ||

4
test/CodeGen/Hexagon/cext-check.ll
View File

@ -2,9 +2,9 @@
; Check that we constant extended instructions only when necessary. ; Check that we constant extended instructions only when necessary.
define i32 @cext_test1(i32* %a) nounwind { define i32 @cext_test1(i32* %a) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+##8000) ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##8000)
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000) ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+##4092) ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##4092)
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300) ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300)
entry: entry:
%0 = load i32* %a, align 4 %0 = load i32* %a, align 4

12
test/MC/Disassembler/Hexagon/ld.txt
View File

@ -38,3 +38,15 @@
0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47 0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47
# CHECK: p3 = r5 # CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42) # CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42)
0xb1 0xc2 0x95 0x91
# CHECK: r17 = memw(r21 + #84)
0xb1 0xda 0x95 0x41
# CHECK: if (p3) r17 = memw(r21 + #84)
0xb1 0xda 0x95 0x45
# CHECK: if (!p3) r17 = memw(r21 + #84)
0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x43
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = memw(r21 + #84)
0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memw(r21 + #84)