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https://github.com/c64scene-ar/llvm-6502.git
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[SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.
Also, pass fp128 arguments to varargs through integer registers if necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
036c045ac9
commit
5b9918957a
@ -80,11 +80,14 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
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static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT, CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) &&
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assert((LocVT == MVT::f32 || LocVT == MVT::f128
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|| LocVT.getSizeInBits() == 64) &&
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"Can't handle non-64 bits locations");
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// Stack space is allocated for all arguments starting from [%fp+BIAS+128].
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unsigned Offset = State.AllocateStack(8, 8);
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unsigned size = (LocVT == MVT::f128) ? 16 : 8;
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unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
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unsigned Offset = State.AllocateStack(size, alignment);
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unsigned Reg = 0;
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if (LocVT == MVT::i64 && Offset < 6*8)
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@ -96,6 +99,9 @@ static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
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else if (LocVT == MVT::f32 && Offset < 16*8)
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// Promote floats to %f1, %f3, ...
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Reg = SP::F1 + Offset/4;
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else if (LocVT == MVT::f128 && Offset < 16*8)
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// Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
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Reg = SP::Q0 + Offset/16;
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// Promote to register when possible, otherwise use the stack slot.
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if (Reg) {
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@ -998,9 +1004,10 @@ static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
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ArrayRef<ISD::OutputArg> Outs) {
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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const CCValAssign &VA = ArgLocs[i];
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MVT ValTy = VA.getLocVT();
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// FIXME: What about f32 arguments? C promotes them to f64 when calling
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// varargs functions.
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if (!VA.isRegLoc() || VA.getLocVT() != MVT::f64)
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if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
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continue;
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// The fixed arguments to a varargs function still go in FP registers.
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if (Outs[VA.getValNo()].IsFixed)
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@ -1010,15 +1017,25 @@ static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
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CCValAssign NewVA;
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// Determine the offset into the argument array.
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unsigned Offset = 8 * (VA.getLocReg() - SP::D0);
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unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
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unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
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unsigned Offset = argSize * (VA.getLocReg() - firstReg);
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assert(Offset < 16*8 && "Offset out of range, bad register enum?");
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if (Offset < 6*8) {
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// This argument should go in %i0-%i5.
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unsigned IReg = SP::I0 + Offset/8;
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// Full register, just bitconvert into i64.
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NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
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IReg, MVT::i64, CCValAssign::BCvt);
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if (ValTy == MVT::f64)
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// Full register, just bitconvert into i64.
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NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
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IReg, MVT::i64, CCValAssign::BCvt);
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else {
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assert(ValTy == MVT::f128 && "Unexpected type!");
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// Full register, just bitconvert into i128 -- We will lower this into
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// two i64s in LowerCall_64.
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NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
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IReg, MVT::i128, CCValAssign::BCvt);
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}
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} else {
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// This needs to go to memory, we're out of integer registers.
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NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
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@ -1094,11 +1111,46 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::BCvt:
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Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
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// fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
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// SPARC does not support i128 natively. Lower it into two i64, see below.
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if (!VA.needsCustom() || VA.getValVT() != MVT::f128
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|| VA.getLocVT() != MVT::i128)
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Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
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break;
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}
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if (VA.isRegLoc()) {
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if (VA.needsCustom() && VA.getValVT() == MVT::f128
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&& VA.getLocVT() == MVT::i128) {
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// Store and reload into the interger register reg and reg+1.
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unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
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unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
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SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
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SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
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HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
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HiPtrOff);
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SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
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LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
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LoPtrOff);
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// Store to %sp+BIAS+128+Offset
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SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
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MachinePointerInfo(),
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false, false, 0);
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// Load into Reg and Reg+1
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SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
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MachinePointerInfo(),
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false, false, false, 0);
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SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
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MachinePointerInfo(),
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false, false, false, 0);
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RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
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Hi64));
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RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
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Lo64));
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continue;
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}
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// The custom bit on an i32 return value indicates that it should be
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// passed in the high bits of the register.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
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@ -411,3 +411,33 @@ entry:
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}
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declare i32 @use_buf(i32, i8*)
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; CHECK-LABEL: test_fp128_args
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; CHECK-DAG: std %f0, [%fp+{{.+}}]
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; CHECK-DAG: std %f2, [%fp+{{.+}}]
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; CHECK-DAG: std %f6, [%fp+{{.+}}]
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; CHECK-DAG: std %f4, [%fp+{{.+}}]
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; CHECK: add %fp, [[Offset:[0-9]+]], %o0
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; CHECK: call _Qp_add
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; CHECK: ldd [%fp+[[Offset]]], %f0
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define fp128 @test_fp128_args(fp128 %a, fp128 %b) {
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entry:
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%0 = fadd fp128 %a, %b
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ret fp128 %0
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}
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declare i64 @receive_fp128(i64 %a, ...)
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; CHECK-LABEL: test_fp128_variable_args
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; CHECK-DAG: std %f4, [%sp+[[Offset0:[0-9]+]]]
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; CHECK-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
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; CHECK-DAG: ldx [%sp+[[Offset0]]], %o2
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; CHECK-DAG: ldx [%sp+[[Offset1]]], %o3
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; CHECK: call receive_fp128
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define i64 @test_fp128_variable_args(i64 %a, fp128 %b) {
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entry:
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%0 = call i64 (i64, ...)* @receive_fp128(i64 %a, fp128 %b)
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ret i64 %0
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}
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