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https://github.com/c64scene-ar/llvm-6502.git
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temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
a51d89ce16
commit
5bcb8a6112
@ -180,9 +180,6 @@ private:
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SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag, bool IsThumb2);
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SDNode *SelectConcatVector(SDNode *N);
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@ -1644,92 +1641,6 @@ SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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return 0;
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}
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/// OptimizeCMOVSoImmOp - It's possible to save an instruction or two be
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/// recognizing that the TST and AND instructions perform the same function
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/// (they "and" the two values). See inside for more details.
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SDNode *ARMDAGToDAGISel::
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OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag,
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bool IsThumb2) {
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// Convert:
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//
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// tst.w r0, #256
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// mvn r0, #25
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// it eq
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// moveq r0, #0
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//
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// into:
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//
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// ands.w r0, r0, #256
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// it ne
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// mvnne.w r0, #25
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//
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if (InFlag.getOpcode() != ARMISD::CMPZ ||
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InFlag.getOperand(0).getOpcode() != ISD::AND)
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return 0;
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// The true value needs to be zero, as that's the result of the AND
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// instruction.
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ConstantSDNode *True = dyn_cast<ConstantSDNode>(TrueVal);
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if (!True || True->getZExtValue() != 0)
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return 0;
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// Bail if the false value isn't an immediate.
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ConstantSDNode *False = dyn_cast<ConstantSDNode>(FalseVal);
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if (!False)
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return 0;
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bool UseMVN = false;
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if ((IsThumb2 && !Pred_t2_so_imm(FalseVal.getNode())) ||
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(!IsThumb2 && !Pred_so_imm(FalseVal.getNode()))) {
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// The false value isn't a proper immediate. Check to see if we can use the
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// bitwise NOT version.
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if ((IsThumb2 && ARM_AM::getT2SOImmVal(~False->getZExtValue()) != -1) ||
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(!IsThumb2 && ARM_AM::getSOImmVal(~False->getZExtValue()) != -1)) {
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UseMVN = true;
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FalseVal = CurDAG->getTargetConstant(~False->getZExtValue(), MVT::i32);
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} else {
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return 0;
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}
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} else {
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FalseVal = CurDAG->getTargetConstant(False->getZExtValue(), MVT::i32);
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}
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// A comparison against zero corresponds with the flag AND sets if the result
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// is zero.
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ConstantSDNode *CmpVal = dyn_cast<ConstantSDNode>(InFlag.getOperand(1));
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if (!CmpVal || CmpVal->getZExtValue() != 0)
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return 0;
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ARMCC::CondCodes NegCC = ARMCC::getOppositeCondition(CCVal);
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SDValue OrigAnd = InFlag.getOperand(0);
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SDValue NewAnd =
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CurDAG->getNode(ARMISD::AND, N->getDebugLoc(),
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CurDAG->getVTList(OrigAnd.getValueType(), MVT::Flag),
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OrigAnd->getOperand(0), OrigAnd->getOperand(1));
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unsigned Opcode = !UseMVN ?
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(IsThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi) :
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(IsThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi);
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SDValue Ops[] = {
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NewAnd.getValue(0),
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FalseVal,
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CurDAG->getTargetConstant(NegCC, MVT::i32),
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CCR, NewAnd.getValue(1)
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};
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SDNode *ResNode = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, Ops, 5);
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// Manually run "Select" on the newly created "ARMISD::AND" node to make
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// sure that it's converted properly.
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SDNode *AndNode = Select(NewAnd.getNode());
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if (AndNode && NewAnd.getNode() != AndNode &&
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NewAnd.getNode()->getOpcode() != ISD::DELETED_NODE)
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ReplaceUses(NewAnd.getNode(), AndNode);
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return ResNode;
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}
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SDNode *ARMDAGToDAGISel::
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SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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@ -1738,10 +1649,6 @@ SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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return 0;
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if (Pred_t2_so_imm(TrueVal.getNode())) {
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SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR,
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InFlag, true);
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if (ResNode) return ResNode;
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SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
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@ -1759,10 +1666,6 @@ SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
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return 0;
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if (Pred_so_imm(TrueVal.getNode())) {
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SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR,
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InFlag, false);
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if (ResNode) return ResNode;
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SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
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@ -2419,14 +2419,6 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
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RegConstraint<"$false = $dst">, UnaryDP {
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let Inst{25} = 1;
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}
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def MVNCCi : AI1<0b1111, (outs GPR:$dst),
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(ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
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"mvn", "\t$dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false,so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst">, UnaryDP {
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let Inst{25} = 0;
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}
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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@ -2195,18 +2195,6 @@ def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
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let Inst{15} = 0;
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}
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def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
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IIC_iCMOVi, "mvn", ".w\t$dst, $true",
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[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst"> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = 0b0011;
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let Inst{20} = 0; // The S bit.
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let Inst{19-16} = 0b1111; // Rn
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let Inst{15} = 0;
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}
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class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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@ -1,12 +0,0 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
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define i32 @f1(i32 %t) nounwind {
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; CHECK: f1
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; CHECK-NOT: tst
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; CHECK: and
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; CHECK: mvnne
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%and = and i32 %t, 256
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%tobool = icmp eq i32 %and, 0
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%retval.0 = select i1 %tobool, i32 0, i32 -26
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ret i32 %retval.0
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}
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@ -1,13 +0,0 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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define i32 @f1(i32 %t) nounwind {
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; CHECK: f1
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; CHECK-NOT: tst
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; CHECK: ands
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; CHECK: it ne
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; CHECK: mvnne
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%and = and i32 %t, 256
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%tobool = icmp eq i32 %and, 0
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%retval.0 = select i1 %tobool, i32 0, i32 -26
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ret i32 %retval.0
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}
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