fix a bug where we had an implicit assumption that the

result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-11-06 08:20:59 +00:00
parent 5e262bc943
commit 5bde734598
5 changed files with 40 additions and 29 deletions

View File

@ -877,27 +877,6 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
}
// The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
// synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
// other operand order, swap them.
if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
Name == "xchg")
if (Operands.size() == 3 &&
static_cast<X86Operand*>(Operands[1])->isMem() &&
static_cast<X86Operand*>(Operands[2])->isReg()) {
std::swap(Operands[1], Operands[2]);
}
// The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
// synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
// other operand order, swap them.
if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
Name == "test")
if (Operands.size() == 3 &&
static_cast<X86Operand*>(Operands[1])->isReg() &&
static_cast<X86Operand*>(Operands[2])->isMem()) {
std::swap(Operands[1], Operands[2]);
}
// The assembler accepts these instructions with no operand as a synonym for
// an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".

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@ -1060,17 +1060,14 @@ let Constraints = "$val = $dst" in {
def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
"xchg{b}\t{$val, $ptr|$ptr, $val}",
[(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
(ins GR16:$val, i16mem:$ptr),
def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
"xchg{w}\t{$val, $ptr|$ptr, $val}",
[(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
OpSize;
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$val, i32mem:$ptr),
def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
"xchg{l}\t{$val, $ptr|$ptr, $val}",
[(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$val,i64mem:$ptr),
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
"xchg{q}\t{$val, $ptr|$ptr, $val}",
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
@ -1414,4 +1411,15 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
// Note: No GR32->GR64 movzx form.
// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>;
def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;

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@ -1177,7 +1177,8 @@ void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II,
if (CGA.ResultOperands[i].Name == OperandName) {
// It's safe to go with the first one we find, because CodeGenInstAlias
// validates that all operands with the same name have the same record.
Op.Class = getOperandClass(CGA.ResultInst->Operands[i]);
unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i);
Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]);
Op.SrcOpName = OperandName;
return;
}

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@ -459,3 +459,21 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
" instruction expects " + utostr(ResultInst->Operands.size())+
" operands!");
}
/// getResultInstOperandIndexForResultOperandIndex - Given an index into the
/// ResultOperands array, translate it to a valid index in ResultInst's
/// operand list.
unsigned CodeGenInstAlias::
getResultInstOperandIndexForResultOperandIndex(unsigned OpNo) const {
unsigned OpIdx = 0;
for (unsigned i = 0;; ++i) {
assert(i != ResultInst->Operands.size() && "Didn't find entry");
if (ResultInst->Operands[i].getTiedRegister() != -1)
continue;
if (OpIdx == OpNo) return i;
++OpIdx;
}
}

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@ -277,6 +277,11 @@ namespace llvm {
std::vector<ResultOperand> ResultOperands;
CodeGenInstAlias(Record *R, CodeGenTarget &T);
/// getResultInstOperandIndexForResultOperandIndex - Given an index into the
/// ResultOperands array, translate it to a valid index in ResultInst's
/// operand list.
unsigned getResultInstOperandIndexForResultOperandIndex(unsigned i) const;
};
}