6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-06 21:27:23 +00:00
Code Issues Projects Releases Wiki Activity

Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188868 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2013-08-21 05:57:45 +00:00
parent ec7b5e9290
commit 5bdf397e25
2 changed files with 11 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@@ -786,8 +786,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
VEX_4V = getVEXRegisterEncoding(MI, CurOp); VEX_4V = getVEXRegisterEncoding(MI, CurOp);
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
EVEX_V2 = 0x0; EVEX_V2 = 0x0;
CurOp++;
} }
CurOp++;
if (HasEVEX_K) if (HasEVEX_K)
EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);

21
lib/Target/X86/X86CodeEmitter.cpp
View File

@@ -982,16 +982,13 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
// FMA4: // FMA4:
// dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
// dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_R = 0x0; VEX_R = 0x0;
CurOp++;
if (HasVEX_4V) { if (HasVEX_4V) {
if (HasMemOp4) VEX_4V = getVEXRegisterEncoding(MI, CurOp);
VEX_4V = getVEXRegisterEncoding(MI, 1); CurOp++;
else
// FMA3 instructions operands are dst, src1, src2, src3
// dst and src1 are the same and not encoded separately
VEX_4V = getVEXRegisterEncoding(MI, 2);
} }
if (X86II::isX86_64ExtendedReg( if (X86II::isX86_64ExtendedReg(
@@ -1002,7 +999,7 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
VEX_X = 0x0; VEX_X = 0x0;
if (HasVEX_4VOp3) if (HasVEX_4VOp3)
VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1); VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
break; break;
case X86II::MRM0m: case X86II::MRM1m: case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m: case X86II::MRM2m: case X86II::MRM3m:
@@ -1012,7 +1009,7 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
// MemAddr // MemAddr
// src1(VEX_4V), MemAddr // src1(VEX_4V), MemAddr
if (HasVEX_4V) if (HasVEX_4V)
VEX_4V = getVEXRegisterEncoding(MI, 0); VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
if (X86II::isX86_64ExtendedReg( if (X86II::isX86_64ExtendedReg(
MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
@@ -1065,8 +1062,10 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
case X86II::MRM6r: case X86II::MRM7r: case X86II::MRM6r: case X86II::MRM7r:
// MRM0r-MRM7r instructions forms: // MRM0r-MRM7r instructions forms:
// dst(VEX_4V), src(ModR/M), imm8 // dst(VEX_4V), src(ModR/M), imm8
VEX_4V = getVEXRegisterEncoding(MI, 0); VEX_4V = getVEXRegisterEncoding(MI, CurOp);
if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) CurOp++;
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_B = 0x0; VEX_B = 0x0;
break; break;
default: // RawFrm default: // RawFrm