mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 22:07:27 +00:00
Clean up mips16 td file in preparation for massive pseudo lowering work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175379 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
4913680168
commit
5be5fa468a
@ -64,10 +64,9 @@ class F2RI16_ins<bits<5> _op, string asmstr,
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//
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// EXT-CCRR Instruction format
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//
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class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
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class FEXT_CCRXI16_ins<string asmstr>:
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MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
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let isCodeGenOnly=1;
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}
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@ -113,9 +112,9 @@ class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
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//
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// CC-RR Instruction format
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//
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class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
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class FCCRR16_ins<string asmstr> :
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MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
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let isCodeGenOnly=1;
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}
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@ -189,24 +188,22 @@ class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
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//
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// EXT-T8I8
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//
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class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_I816<_func, (outs),
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(ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
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!strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
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!strconcat(asmstr, "\t$imm"))),[], itin> {
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class FEXT_T8I816_ins<string asmstr, string asmstr2>:
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MipsPseudo16<(outs),
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(ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
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!strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
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!strconcat(asmstr, "\t$imm"))),[]> {
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let isCodeGenOnly=1;
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}
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//
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// EXT-T8I8I
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//
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class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_I816<_func, (outs),
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(ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
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!strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
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!strconcat(asmstr, "\t$targ"))), [], itin> {
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class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
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MipsPseudo16<(outs),
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(ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
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!strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
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!strconcat(asmstr, "\t$targ"))), []> {
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let isCodeGenOnly=1;
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}
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//
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@ -255,9 +252,9 @@ class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
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class FRRTR16_ins<string asmstr> :
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MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
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//
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// maybe refactor but need a $zero as a dummy first parameter
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@ -332,11 +329,11 @@ class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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//
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// So this pseudo class only has one operand, i.e. op
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//
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class Sel<bits<5> f1, string op, InstrItinClass itin>:
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MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rt),
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!strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin> {
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let isCodeGenOnly=1;
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class Sel<string op>:
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MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rt),
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!strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
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//let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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}
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@ -355,13 +352,12 @@ class Sel<bits<5> f1, string op, InstrItinClass itin>:
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// move $rd, $rs
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//
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//
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class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
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InstrItinClass itin>:
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MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rl, simm16:$imm),
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!strconcat(op2,
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!strconcat("\t$rl, $imm\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> {
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class SeliT<string op1, string op2>:
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MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rl, simm16:$imm),
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!strconcat(op2,
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!strconcat("\t$rl, $imm\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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}
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@ -378,13 +374,13 @@ class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
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// move $rd, $rs
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//
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//
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class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
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InstrItinClass itin>:
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MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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class SelT<string op1, string op2>:
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MipsPseudo16<(outs CPU16Regs:$rd_),
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(ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rl, CPU16Regs:$rr),
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!strconcat(op2,
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!strconcat("\t$rl, $rr\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> {
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!strconcat(op2,
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!strconcat("\t$rl, $rr\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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}
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@ -434,6 +430,7 @@ class MayStore {
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}
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//
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// Format: ADDIU rx, immediate MIPS16e
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// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
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// To add a constant to a 32-bit integer.
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@ -521,18 +518,18 @@ def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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//
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def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
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def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
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def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
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def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
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def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
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cbranch16;
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def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
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def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
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def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
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def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
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def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
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def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
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def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
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def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
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cbranch16;
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//
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@ -542,17 +539,17 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
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//
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def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
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def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
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def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
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def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
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def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
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def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
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def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
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def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
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def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
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def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
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def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
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def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
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def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
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cbranch16;
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//
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@ -847,7 +844,7 @@ def SbRxRyOffMemX16:
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// Purpose: if rt==0, do nothing
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// else rs = rt
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//
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def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
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def SelBeqZ: Sel<"beqz">;
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//
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// Format: SelTBteqZCmp rd, rs, rl, rr
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@ -855,7 +852,7 @@ def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
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def SelTBteqZCmp: SelT<"bteqz", "cmp">;
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//
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// Format: SelTBteqZCmpi rd, rs, rl, rr
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@ -863,7 +860,7 @@ def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
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def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
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//
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// Format: SelTBteqZSlt rd, rs, rl, rr
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@ -871,7 +868,7 @@ def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
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def SelTBteqZSlt: SelT<"bteqz", "slt">;
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//
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// Format: SelTBteqZSlti rd, rs, rl, rr
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@ -879,7 +876,7 @@ def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
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def SelTBteqZSlti: SeliT<"bteqz", "slti">;
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//
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// Format: SelTBteqZSltu rd, rs, rl, rr
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@ -887,7 +884,7 @@ def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
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def SelTBteqZSltu: SelT<"bteqz", "sltu">;
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//
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// Format: SelTBteqZSltiu rd, rs, rl, rr
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@ -895,14 +892,14 @@ def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
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// If b==0 then do nothing.
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// if b!=0 then rd = rs
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//
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def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
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def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
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//
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// Format: SelBnez rd, rs, rt
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// Purpose: if rt!=0, do nothing
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// else rs = rt
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//
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def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
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def SelBneZ: Sel<"bnez">;
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//
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// Format: SelTBtneZCmp rd, rs, rl, rr
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@ -910,7 +907,7 @@ def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
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// If b!=0 then do nothing.
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// if b0=0 then rd = rs
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//
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def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
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def SelTBtneZCmp: SelT<"btnez", "cmp">;
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//
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// Format: SelTBtnezCmpi rd, rs, rl, rr
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@ -918,7 +915,7 @@ def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
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def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
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//
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// Format: SelTBtneZSlt rd, rs, rl, rr
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@ -926,7 +923,7 @@ def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
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def SelTBtneZSlt: SelT<"btnez", "slt">;
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//
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// Format: SelTBtneZSlti rd, rs, rl, rr
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@ -934,7 +931,7 @@ def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
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def SelTBtneZSlti: SeliT<"btnez", "slti">;
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//
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// Format: SelTBtneZSltu rd, rs, rl, rr
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@ -942,7 +939,7 @@ def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
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def SelTBtneZSltu: SelT<"btnez", "sltu">;
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//
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// Format: SelTBtneZSltiu rd, rs, rl, rr
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@ -950,7 +947,7 @@ def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
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// If b!=0 then do nothing.
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// if b==0 then rd = rs
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//
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def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
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def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
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//
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//
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// Format: SH ry, offset(rx) MIPS16e
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@ -979,14 +976,14 @@ def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
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// Purpose: Set on Less Than Immediate (Extended)
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// To record the result of a less-than comparison with a constant.
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//
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def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
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def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
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//
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// Format: SLTIU rx, immediate MIPS16e
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// Purpose: Set on Less Than Immediate Unsigned (Extended)
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// To record the result of a less-than comparison with a constant.
|
||||
//
|
||||
def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
|
||||
def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
|
||||
|
||||
//
|
||||
// Format: SLT rx, ry MIPS16e
|
||||
@ -995,18 +992,18 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
|
||||
//
|
||||
def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
|
||||
|
||||
def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
|
||||
def SltCCRxRy16: FCCRR16_ins<"slt">;
|
||||
|
||||
// Format: SLTU rx, ry MIPS16e
|
||||
// Purpose: Set on Less Than Unsigned
|
||||
// To record the result of an unsigned less-than comparison.
|
||||
//
|
||||
def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
|
||||
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
|
||||
let isCodeGenOnly=1;
|
||||
}
|
||||
|
||||
|
||||
def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
|
||||
def SltuCCRxRy16: FCCRR16_ins<"sltu">;
|
||||
//
|
||||
// Format: SRAV ry, rx MIPS16e
|
||||
// Purpose: Shift Word Right Arithmetic Variable
|
||||
|
||||
Loading…
Reference in New Issue
Block a user