From 5c062ad92672f22e61a4b20a9954af3db3b72bd6 Mon Sep 17 00:00:00 2001
From: Silviu Baranga <silviu.baranga@arm.com>
Date: Tue, 20 Mar 2012 15:54:56 +0000
Subject: [PATCH] The ARM instructions that have an unpredictable behavior when
 the pc register operand is given now fail with soft fail. Modified the
 regression tests to reflect this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrInfo.td                         |  4 ++--
 lib/Target/ARM/Disassembler/ARMDisassembler.cpp        | 10 ++++++++--
 ...d-LSL-regform.txt => unpredictable-LSL-regform.txt} |  4 +++-
 .../{invalid-RSC-arm.txt => unpredictable-RSC-arm.txt} |  4 +++-
 ...invalid-SSAT-arm.txt => unpredictable-SSAT-arm.txt} |  4 +++-
 ...lid-STRBrs-arm.txt => unpredictable-STRBrs-arm.txt} |  4 +++-
 ...lid-UQADD8-arm.txt => unpredictable-UQADD8-arm.txt} |  6 +++++-
 7 files changed, 27 insertions(+), 9 deletions(-)
 rename test/MC/Disassembler/ARM/{invalid-LSL-regform.txt => unpredictable-LSL-regform.txt} (80%)
 rename test/MC/Disassembler/ARM/{invalid-RSC-arm.txt => unpredictable-RSC-arm.txt} (79%)
 rename test/MC/Disassembler/ARM/{invalid-SSAT-arm.txt => unpredictable-SSAT-arm.txt} (79%)
 rename test/MC/Disassembler/ARM/{invalid-STRBrs-arm.txt => unpredictable-STRBrs-arm.txt} (78%)
 rename test/MC/Disassembler/ARM/{invalid-UQADD8-arm.txt => unpredictable-UQADD8-arm.txt} (79%)

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3b647cdee22..a594271c94e 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -4128,8 +4128,8 @@ multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
     let Inst{3-0} = shift{3-0};
   }
 
-  def rsr : AsI1<opcod, (outs GPR:$Rd),
-               (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
+  def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
+               (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
                iis, opc, "\t$Rd, $Rn, $shift", []>,
                RegConstraint<"$Rn = $Rd"> {
     bits<4> Rd;
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 86f4d7b6765..e52e6c7f077 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -869,8 +869,14 @@ static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 static DecodeStatus
 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                            uint64_t Address, const void *Decoder) {
-  if (RegNo == 15) return MCDisassembler::Fail;
-  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
+  DecodeStatus S = MCDisassembler::Success;
+  
+  if (RegNo == 15) 
+    S = MCDisassembler::SoftFail;
+
+  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+
+  return S;
 }
 
 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
similarity index 80%
rename from test/MC/Disassembler/ARM/invalid-LSL-regform.txt
rename to test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
index 6a1f11faf23..f7d6bc6edcf 100644
--- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
+++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
 
 # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
@@ -8,4 +8,6 @@
 #
 # A8.6.89 LSL (register)
 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+
+# CHECK: warning: potentially undefined instruction encoding
 0x12 0xf1 0xa0 0xe1
diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt
similarity index 79%
rename from test/MC/Disassembler/ARM/invalid-RSC-arm.txt
rename to test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt
index 096b909bc6d..5b136109499 100644
--- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
+++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
 
 # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
@@ -6,4 +6,6 @@
 # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
 # -------------------------------------------------------------------------------------------------
 # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+
+# CHECK: warning: potentially undefined instruction encoding
 0x5f 0xf8 0xe4 0x30
diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt
similarity index 79%
rename from test/MC/Disassembler/ARM/invalid-SSAT-arm.txt
rename to test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt
index b236f8ef4d2..874378ed024 100644
--- a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt
+++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
 
 # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
@@ -8,4 +8,6 @@
 #
 # A8.6.183 SSAT
 # if d == 15 || n == 15 then UNPREDICTABLE;
+
+# CHECK:warning: potentially undefined instruction encoding
 0x1a 0xf4 0xa0 0xe6
diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt
similarity index 78%
rename from test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt
rename to test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt
index d3998bdc09a..fef6125d283 100644
--- a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt
+++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
 
 # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
@@ -7,4 +7,6 @@
 # -------------------------------------------------------------------------------------------------
 #
 # if t == 15 then UNPREDICTABLE
+
+# CHECK: warning: potentially undefined instruction encoding
 0x00 0xf0 0xcf 0xe7
diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt
similarity index 79%
rename from test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt
rename to test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt
index fb3e71106c9..4c4c9abed2f 100644
--- a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt
+++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
 
 # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4)
 #  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
@@ -10,3 +10,7 @@
 #
 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 0x9f 0x5f 0x66 0xe6
+
+# CHECK: warning: potentially undefined
+# CHECK: uqadd8	r5, r6, pc
+