mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
parent
feb5bfbc6b
commit
5c376ff9f0
@ -1245,6 +1245,17 @@ class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
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let Inst{7-4} = op7_4;
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}
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// With selective bit(s) from op7_4 specified by subclasses.
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class NLdStLN<bit op23, bits<2> op21_20, bits<4> op11_8,
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dag oops, dag iops, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, asm, cstr, pattern> {
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let Inst{31-24} = 0b11110100;
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let Inst{23} = op23;
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let Inst{21-20} = op21_20;
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let Inst{11-8} = op11_8;
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}
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class NDataI<dag oops, dag iops, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, asm, cstr, pattern> {
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@ -280,66 +280,107 @@ def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
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// VLD2LN : Vector Load (single 2-element structure to one lane)
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class VLD2LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VLD2,
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!strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2", []>;
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: NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VLD2,
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!strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2", []>;
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// vld2 to single-spaced registers.
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def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
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def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">;
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def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">;
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def VLD2LNd16 : VLD2LN<0b0101, "vld2.16"> {
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let Inst{5} = 0;
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}
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def VLD2LNd32 : VLD2LN<0b1001, "vld2.32"> {
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let Inst{6} = 0;
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}
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// vld2 to double-spaced even registers.
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def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">;
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def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">;
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def VLD2LNq16a: VLD2LN<0b0101, "vld2.16"> {
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let Inst{5} = 1;
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}
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def VLD2LNq32a: VLD2LN<0b1001, "vld2.32"> {
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let Inst{6} = 1;
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}
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// vld2 to double-spaced odd registers.
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def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">;
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def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">;
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def VLD2LNq16b: VLD2LN<0b0101, "vld2.16"> {
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let Inst{5} = 1;
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}
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def VLD2LNq32b: VLD2LN<0b1001, "vld2.32"> {
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let Inst{6} = 1;
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}
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// VLD3LN : Vector Load (single 3-element structure to one lane)
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class VLD3LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VLD3,
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!strconcat(OpcodeStr,
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"\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
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: NLdStLN<1,0b10,op11_8, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VLD3,
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!strconcat(OpcodeStr,
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"\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
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def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">;
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def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">;
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def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">;
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// vld3 to single-spaced registers.
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def VLD3LNd8 : VLD3LN<0b0010, "vld3.8"> {
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let Inst{4} = 0;
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}
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def VLD3LNd16 : VLD3LN<0b0110, "vld3.16"> {
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let Inst{5-4} = 0b00;
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}
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def VLD3LNd32 : VLD3LN<0b1010, "vld3.32"> {
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let Inst{6-4} = 0b000;
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}
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// vld3 to double-spaced even registers.
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def VLD3LNq16a: VLD3LN<0b0110, "vld3.16">;
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def VLD3LNq32a: VLD3LN<0b1010, "vld3.32">;
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def VLD3LNq16a: VLD3LN<0b0110, "vld3.16"> {
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let Inst{5-4} = 0b10;
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}
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def VLD3LNq32a: VLD3LN<0b1010, "vld3.32"> {
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let Inst{6-4} = 0b100;
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}
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// vld3 to double-spaced odd registers.
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def VLD3LNq16b: VLD3LN<0b0110, "vld3.16">;
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def VLD3LNq32b: VLD3LN<0b1010, "vld3.32">;
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def VLD3LNq16b: VLD3LN<0b0110, "vld3.16"> {
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let Inst{5-4} = 0b10;
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}
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def VLD3LNq32b: VLD3LN<0b1010, "vld3.32"> {
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let Inst{6-4} = 0b100;
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}
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// VLD4LN : Vector Load (single 4-element structure to one lane)
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class VLD4LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b10,op11_8,0b0000,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VLD4,
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!strconcat(OpcodeStr,
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"\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
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: NLdStLN<1,0b10,op11_8,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VLD4,
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!strconcat(OpcodeStr,
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"\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
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// vld4 to single-spaced registers.
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def VLD4LNd8 : VLD4LN<0b0011, "vld4.8">;
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def VLD4LNd16 : VLD4LN<0b0111, "vld4.16">;
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def VLD4LNd32 : VLD4LN<0b1011, "vld4.32">;
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def VLD4LNd16 : VLD4LN<0b0111, "vld4.16"> {
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let Inst{5} = 0;
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}
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def VLD4LNd32 : VLD4LN<0b1011, "vld4.32"> {
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let Inst{6} = 0;
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}
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// vld4 to double-spaced even registers.
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def VLD4LNq16a: VLD4LN<0b0111, "vld4.16">;
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def VLD4LNq32a: VLD4LN<0b1011, "vld4.32">;
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def VLD4LNq16a: VLD4LN<0b0111, "vld4.16"> {
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let Inst{5} = 1;
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}
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def VLD4LNq32a: VLD4LN<0b1011, "vld4.32"> {
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let Inst{6} = 1;
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}
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// vld4 to double-spaced odd registers.
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def VLD4LNq16b: VLD4LN<0b0111, "vld4.16">;
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def VLD4LNq32b: VLD4LN<0b1011, "vld4.32">;
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def VLD4LNq16b: VLD4LN<0b0111, "vld4.16"> {
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let Inst{5} = 1;
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}
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def VLD4LNq32b: VLD4LN<0b1011, "vld4.32"> {
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let Inst{6} = 1;
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}
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// VLD1DUP : Vector Load (single element to all lanes)
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// VLD2DUP : Vector Load (single 2-element structure to all lanes)
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@ -463,64 +504,105 @@ def VST4q32b : VST4WB<0b1000, "vst4.32">;
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// VST2LN : Vector Store (single 2-element structure from one lane)
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class VST2LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b00,op11_8,0b0000, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VST,
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!strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
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"", []>;
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: NLdStLN<1,0b00,op11_8, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
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IIC_VST,
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!strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
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"", []>;
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// vst2 to single-spaced registers.
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def VST2LNd8 : VST2LN<0b0001, "vst2.8">;
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def VST2LNd16 : VST2LN<0b0101, "vst2.16">;
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def VST2LNd32 : VST2LN<0b1001, "vst2.32">;
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def VST2LNd16 : VST2LN<0b0101, "vst2.16"> {
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let Inst{5} = 0;
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}
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def VST2LNd32 : VST2LN<0b1001, "vst2.32"> {
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let Inst{6} = 0;
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}
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// vst2 to double-spaced even registers.
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def VST2LNq16a: VST2LN<0b0101, "vst2.16">;
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def VST2LNq32a: VST2LN<0b1001, "vst2.32">;
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def VST2LNq16a: VST2LN<0b0101, "vst2.16"> {
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let Inst{5} = 1;
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}
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def VST2LNq32a: VST2LN<0b1001, "vst2.32"> {
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let Inst{6} = 1;
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}
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// vst2 to double-spaced odd registers.
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def VST2LNq16b: VST2LN<0b0101, "vst2.16">;
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def VST2LNq32b: VST2LN<0b1001, "vst2.32">;
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def VST2LNq16b: VST2LN<0b0101, "vst2.16"> {
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let Inst{5} = 1;
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}
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def VST2LNq32b: VST2LN<0b1001, "vst2.32"> {
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let Inst{6} = 1;
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}
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// VST3LN : Vector Store (single 3-element structure from one lane)
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class VST3LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b00,op11_8,0b0000, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VST,
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!strconcat(OpcodeStr,
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"\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
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: NLdStLN<1,0b00,op11_8, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VST,
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!strconcat(OpcodeStr,
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"\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
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def VST3LNd8 : VST3LN<0b0010, "vst3.8">;
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def VST3LNd16 : VST3LN<0b0110, "vst3.16">;
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def VST3LNd32 : VST3LN<0b1010, "vst3.32">;
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// vst3 to single-spaced registers.
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def VST3LNd8 : VST3LN<0b0010, "vst3.8"> {
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let Inst{4} = 0;
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}
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def VST3LNd16 : VST3LN<0b0110, "vst3.16"> {
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let Inst{5-4} = 0b00;
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}
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def VST3LNd32 : VST3LN<0b1010, "vst3.32"> {
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let Inst{6-4} = 0b000;
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}
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// vst3 to double-spaced even registers.
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def VST3LNq16a: VST3LN<0b0110, "vst3.16">;
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def VST3LNq32a: VST3LN<0b1010, "vst3.32">;
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def VST3LNq16a: VST3LN<0b0110, "vst3.16"> {
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let Inst{5-4} = 0b10;
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}
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def VST3LNq32a: VST3LN<0b1010, "vst3.32"> {
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let Inst{6-4} = 0b100;
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}
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// vst3 to double-spaced odd registers.
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def VST3LNq16b: VST3LN<0b0110, "vst3.16">;
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def VST3LNq32b: VST3LN<0b1010, "vst3.32">;
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def VST3LNq16b: VST3LN<0b0110, "vst3.16"> {
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let Inst{5-4} = 0b10;
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}
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def VST3LNq32b: VST3LN<0b1010, "vst3.32"> {
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let Inst{6-4} = 0b100;
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}
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// VST4LN : Vector Store (single 4-element structure from one lane)
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class VST4LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b00,op11_8,0b0000, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VST,
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!strconcat(OpcodeStr,
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"\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
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"", []>;
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: NLdStLN<1,0b00,op11_8, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
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nohash_imm:$lane), IIC_VST,
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!strconcat(OpcodeStr,
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"\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
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"", []>;
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// vst4 to single-spaced registers.
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def VST4LNd8 : VST4LN<0b0011, "vst4.8">;
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def VST4LNd16 : VST4LN<0b0111, "vst4.16">;
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def VST4LNd32 : VST4LN<0b1011, "vst4.32">;
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def VST4LNd16 : VST4LN<0b0111, "vst4.16"> {
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let Inst{5} = 0;
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}
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def VST4LNd32 : VST4LN<0b1011, "vst4.32"> {
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let Inst{6} = 0;
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}
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// vst4 to double-spaced even registers.
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def VST4LNq16a: VST4LN<0b0111, "vst4.16">;
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def VST4LNq32a: VST4LN<0b1011, "vst4.32">;
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def VST4LNq16a: VST4LN<0b0111, "vst4.16"> {
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let Inst{5} = 1;
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}
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def VST4LNq32a: VST4LN<0b1011, "vst4.32"> {
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let Inst{6} = 1;
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}
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// vst4 to double-spaced odd registers.
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def VST4LNq16b: VST4LN<0b0111, "vst4.16">;
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def VST4LNq32b: VST4LN<0b1011, "vst4.32">;
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def VST4LNq16b: VST4LN<0b0111, "vst4.16"> {
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let Inst{5} = 1;
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}
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def VST4LNq32b: VST4LN<0b1011, "vst4.32"> {
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let Inst{6} = 1;
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}
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} // mayStore = 1, hasExtraSrcRegAllocReq = 1
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