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Implement the code for PowerPC/inverted-bool-compares.ll, even though it

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that testcase still does not pass with the dag combiner.  This is because
not all forms of br* are folded yet.

Also, when we combine a node into another one, delete the node immediately
instead of waiting for the node to potentially come up in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23632 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-05 06:11:08 +00:00
parent d48050aa15
commit 5c46f74ec7
1 changed files with 16 additions and 1 deletions
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17
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -313,6 +313,9 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
// Nodes can end up on the worklist more than once. Make sure we do
// not process a node that has been replaced.
removeFromWorkList(N);
// Finally, since the node is now dead, remove it from the graph.
DAG.DeleteNode(N);
}
}
}
@ -1546,7 +1549,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
ExtDstTy),
Cond);
}
uint64_t MinVal, MaxVal;
unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
if (ISD::isSignedIntSetCC(Cond)) {
@ -1682,6 +1685,18 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
}
}
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
if (N0.getOpcode() == ISD::XOR)
if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
// If we know that all of the inverted bits are zero, don't bother
// performing the inversion.
if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
return DAG.getSetCC(VT, N0.getOperand(0),
DAG.getConstant(XORC->getValue()^RHSC->getValue(),
N0.getValueType()), Cond);
}
// Simplify (X+Z) == X --> Z == 0
if (N0.getOperand(0) == N1)
return DAG.getSetCC(VT, N0.getOperand(1),