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[cleanup] Hoist the promotion dispatch logic into the promote function

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so that we can use return to express it more cleanly and avoid so many
nested switch statements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-07-02 03:07:15 +00:00
parent 42caaf8e17
commit 5c65424138
1 changed files with 22 additions and 23 deletions
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45
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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@ -281,27 +281,11 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
case TargetLowering::Promote:
switch (Op.getOpcode()) {
default:
// "Promote" the operation by bitcasting
Result = Promote(Op);
Changed = true;
break;
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
// "Promote" the operation by extending the operand.
Result = PromoteINT_TO_FP(Op);
Changed = true;
break;
case ISD::FP_TO_UINT:
case ISD::FP_TO_SINT:
// Promote the operation by extending the operand.
Result = PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
Changed = true;
break;
}
Result = Promote(Op);
Changed = true;
break;
case TargetLowering::Legal:
break;
case TargetLowering::Legal: break;
case TargetLowering::Custom: {
SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
if (Tmp1.getNode()) {
@ -343,9 +327,24 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
}
SDValue VectorLegalizer::Promote(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
// For a few operations there is a specific concept for promotion based on
// the operand's type.
switch (Op.getOpcode()) {
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
// "Promote" the operation by extending the operand.
return PromoteINT_TO_FP(Op);
break;
case ISD::FP_TO_UINT:
case ISD::FP_TO_SINT:
// Promote the operation by extending the operand.
return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
break;
}
// The rest of the time, vector "promotion" is basically just bitcasting and
// doing the operation in a different type. For example, x86 promotes
// ISD::AND on v2i32 to v1i64.
MVT VT = Op.getSimpleValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");