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ARM: Refactor instaliases using TableGen support for #NAME#.
Now that TableGen supports references to NAME w/o it being explicitly referenced in the definition's own name, use that to simplify assembly InstAlias definitions in multiclasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161218 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -530,7 +530,7 @@ class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
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/// changed to modify CPSR.
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multiclass T2I_bin_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, string baseOpc, bit Commutable = 0,
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PatFrag opnode, bit Commutable = 0,
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string wide = ""> {
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// shifted imm
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def ri : T2sTwoRegImm<
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@ -566,15 +566,15 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
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// Assembly aliases for optional destination operand when it's the same
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// as the source operand.
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def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
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(!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
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t2_so_imm:$imm, pred:$p,
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
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(!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
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(!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
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rGPR:$Rm, pred:$p,
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
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(!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
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(!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
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t2_so_reg:$shift, pred:$p,
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cc_out:$s)>;
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}
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@ -583,36 +583,30 @@ multiclass T2I_bin_irs<bits<4> opcod, string opc,
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// the ".w" suffix to indicate that they are wide.
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multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, string baseOpc, bit Commutable = 0> :
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T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
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PatFrag opnode, bit Commutable = 0> :
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T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
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// Assembler aliases w/ the ".w" suffix.
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def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
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t2_so_imm:$imm, pred:$p,
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cc_out:$s)>;
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(!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
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cc_out:$s)>;
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// Assembler aliases w/o the ".w" suffix.
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def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
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(!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
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rGPR:$Rm, pred:$p,
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cc_out:$s)>;
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(!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
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(!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
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t2_so_reg:$shift, pred:$p,
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cc_out:$s)>;
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(!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
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pred:$p, cc_out:$s)>;
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// and with the optional destination operand, too.
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def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
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(!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
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t2_so_imm:$imm, pred:$p,
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cc_out:$s)>;
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(!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
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pred:$p, cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
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(!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
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rGPR:$Rm, pred:$p,
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cc_out:$s)>;
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(!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
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cc_out:$s)>;
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def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
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(!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
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t2_so_reg:$shift, pred:$p,
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cc_out:$s)>;
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(!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
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pred:$p, cc_out:$s)>;
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}
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/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
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@ -2215,18 +2209,17 @@ def t2MOVsra_flag : T2TwoRegShiftImm<
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defm t2AND : T2I_bin_w_irs<0b0000, "and",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
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BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
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defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
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BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
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defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
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BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
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defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(and node:$LHS, (not node:$RHS))>,
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"t2BIC">;
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BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
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class T2BitFI<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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@ -2306,8 +2299,7 @@ let Constraints = "$src = $Rd" in {
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defm t2ORN : T2I_bin_irs<0b0011, "orn",
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IIC_iBITi, IIC_iBITr, IIC_iBITsi,
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BinOpFrag<(or node:$LHS, (not node:$RHS))>,
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"t2ORN", 0, "">;
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BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
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/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// unary operation that produces a value. These are predicable and can be
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