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[mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.

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Differential Revision: http://reviews.llvm.org/D5799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek 2014-11-19 13:11:09 +00:00
parent 3629d7559c
commit 5c6c7e3295
3 changed files with 35 additions and 3 deletions
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8
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -31,6 +31,8 @@ def uimm4_andi : Operand<i32> {
let EncoderMethod = "getUImm4AndValue"; let EncoderMethod = "getUImm4AndValue";
} }
def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
def immZExtAndi16 : ImmLeaf<i32, def immZExtAndi16 : ImmLeaf<i32,
[{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
@ -161,7 +163,6 @@ class AddImmUS5<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm), MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> { !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
let Constraints = "$rd = $dst"; let Constraints = "$rd = $dst";
let isCommutable = 1;
} }
class AddImmUR1SP<string opstr, RegisterOperand RO> : class AddImmUR1SP<string opstr, RegisterOperand RO> :
@ -527,6 +528,11 @@ let Predicates = [InMicroMips] in {
// MicroMips arbitrary patterns that map to one or more instructions // MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
(ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
def : MipsPat<(add GPR32:$src, immSExt16:$imm),
(ADDiu_MM GPR32:$src, immSExt16:$imm)>;
def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>; (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
def : MipsPat<(and GPR32:$src, immZExt16:$imm), def : MipsPat<(and GPR32:$src, immZExt16:$imm),

5
lib/Target/Mips/MipsInstrInfo.td
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@ -1096,9 +1096,10 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate) /// Arithmetic Instructions (ALU Immediate)
let AdditionalPredicates = [NotInMicroMips] in {
def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
add>, add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
ADDI_FM<0x9>, IsAsCheapAsAMove; }
def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,

25
test/CodeGen/Mips/micromips-addiu.ll Normal file
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@ -0,0 +1,25 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = global i32 65504, align 4
@y = global i32 60929, align 4
@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
define i32 @main() nounwind {
entry:
%0 = load i32* @x, align 4
%addiu1 = add i32 %0, -7
%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
([7 x i8]* @.str, i32 0, i32 0), i32 %addiu1)
%1 = load i32* @y, align 4
%addiu2 = add i32 %1, 55
%call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
([7 x i8]* @.str, i32 0, i32 0), i32 %addiu2)
ret i32 0
}
declare i32 @printf(i8*, ...)
; CHECK: addius5 ${{[0-9]+}}, -7
; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 55