From 5c7adadf6dfff543de77390dfa305fca8c23f839 Mon Sep 17 00:00:00 2001
From: Colin LeMahieu <colinl@codeaurora.org>
Date: Mon, 8 Dec 2014 17:01:18 +0000
Subject: [PATCH] [Hexagon] Adding packhl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223664 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Target/Hexagon/HexagonInstrInfo.td | 6 ++++++
test/MC/Disassembler/Hexagon/alu32_perm.txt | 2 ++
2 files changed, 8 insertions(+)
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 14dfad1044d..3158adcfa5e 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -204,6 +204,12 @@ def: BinOp32_pat<or, A2_or, i32>;
def: BinOp32_pat<sub, A2_sub, i32>;
def: BinOp32_pat<xor, A2_xor, i32>;
+// A few special cases producing register pairs:
+let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0,
+ isCodeGenOnly = 0 in {
+ def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
+}
+
let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
: ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
diff --git a/test/MC/Disassembler/Hexagon/alu32_perm.txt b/test/MC/Disassembler/Hexagon/alu32_perm.txt
index fce6f8dc68a..2f1d1b65067 100644
--- a/test/MC/Disassembler/Hexagon/alu32_perm.txt
+++ b/test/MC/Disassembler/Hexagon/alu32_perm.txt
@@ -22,3 +22,5 @@
# CHECK: r17 = aslh(r21)
0x11 0xc0 0x35 0x70
# CHECK: r17 = asrh(r21)
+0x10 0xdf 0x95 0xf5
+# CHECK: r17:16 = packhl(r21, r31)