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ARM enclosing curly braces optional on one-register VLD/VST instruction lists.

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'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-15 21:45:55 +00:00
parent 5381cbf4f4
commit 5c984e451d
1 changed files with 23 additions and 2 deletions
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25
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -2487,10 +2487,31 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// parse a vector register list
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
if(Parser.getTok().isNot(AsmToken::LCurly))
SMLoc S = Parser.getTok().getLoc();
// As an extension (to match gas), support a plain D register or Q register
// (without encosing curly braces) as a single or double entry list,
// respectively.
if (Parser.getTok().is(AsmToken::Identifier)) {
int Reg = tryParseRegister();
if (Reg == -1)
return MatchOperand_NoMatch;
SMLoc E = Parser.getTok().getLoc();
if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E));
return MatchOperand_Success;
}
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg);
Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E));
return MatchOperand_Success;
}
Error(S, "vector register expected");
return MatchOperand_ParseFail;
}
if (Parser.getTok().isNot(AsmToken::LCurly))
return MatchOperand_NoMatch;
SMLoc S = Parser.getTok().getLoc();
Parser.Lex(); // Eat '{' token.
SMLoc RegLoc = Parser.getTok().getLoc();