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ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]' rdar://10450488. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2487,10 +2487,31 @@ parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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// parse a vector register list
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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if(Parser.getTok().isNot(AsmToken::LCurly))
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SMLoc S = Parser.getTok().getLoc();
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// As an extension (to match gas), support a plain D register or Q register
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// (without encosing curly braces) as a single or double entry list,
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// respectively.
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if (Parser.getTok().is(AsmToken::Identifier)) {
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int Reg = tryParseRegister();
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if (Reg == -1)
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return MatchOperand_NoMatch;
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SMLoc E = Parser.getTok().getLoc();
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if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
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Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E));
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return MatchOperand_Success;
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}
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if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
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Reg = getDRegFromQReg(Reg);
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Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E));
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return MatchOperand_Success;
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}
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Error(S, "vector register expected");
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return MatchOperand_ParseFail;
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}
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if (Parser.getTok().isNot(AsmToken::LCurly))
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return MatchOperand_NoMatch;
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat '{' token.
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SMLoc RegLoc = Parser.getTok().getLoc();
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