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More shift itins for A9

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2010-04-07 18:21:16 +00:00
parent ecc6406072
commit 5ca13c6ee3
1 changed files with 21 additions and 0 deletions
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21
lib/Target/ARM/ARMScheduleV7.td
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@ -866,6 +866,27 @@ def CortexA9Itineraries : ProcessorItineraries<[
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [3, 1, 1]>, InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
// //
// Quad-register Integer Shift
InstrItinData<IIC_VSHLiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
//
// Double-register Integer Shift (4 cycle)
InstrItinData<IIC_VSHLi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
//
// Quad-register Integer Shift (4 cycle)
InstrItinData<IIC_VSHLi4Q, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
//
// Double-register Integer Binary (4 cycle) // Double-register Integer Binary (4 cycle)
InstrItinData<IIC_VBINi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>, InstrItinData<IIC_VBINi4D, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles // Extra 3 latency cycle since wbck is 6 cycles