6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-13 09:33:50 +00:00
Code Issues Projects Releases Wiki Activity

Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw

Browse Source 
instructions. This simplifies instruction printing and disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-29 22:37:40 +00:00
parent 8ad87ab166
commit 5ca66696e7
8 changed files with 74 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -774,11 +774,6 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
OutContext);
OutStreamer.EmitValue(Expr, OffsetWidth);
}
// Make sure the instruction that follows TBB is 2-byte aligned.
// FIXME: Constant island pass should insert an "ALIGN" instruction instead.
if (MI->getOpcode() == ARM::t2TBB_JT)
EmitAlignment(1);
}
void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
@ -924,15 +919,49 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return;
}
case ARM::t2TBB_JT:
case ARM::t2TBH_JT:
case ARM::t2BR_JT: {
// Lower and emit the instruction itself, then the jump table following it.
MCInst TmpInst;
// FIXME: The branch instruction is really a pseudo. We should xform it
// explicitly.
LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
TmpInst.setOpcode(ARM::tMOVgpr2gpr);
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
// Output the data for the jump table itself
EmitJump2Table(MI);
return;
}
case ARM::t2TBB_JT: {
// Lower and emit the instruction itself, then the jump table following it.
MCInst TmpInst;
TmpInst.setOpcode(ARM::t2TBB);
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
// Output the data for the jump table itself
EmitJump2Table(MI);
// Make sure the next instruction is 2-byte aligned.
EmitAlignment(1);
return;
}
case ARM::t2TBH_JT: {
// Lower and emit the instruction itself, then the jump table following it.
MCInst TmpInst;
TmpInst.setOpcode(ARM::t2TBH);
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
// Output the data for the jump table itself
EmitJump2Table(MI);
return;
}
@ -941,7 +970,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Lower and emit the instruction itself, then the jump table following it.
// mov pc, target
MCInst TmpInst;
unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? ARM::MOVr : ARM::tMOVr;
unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
ARM::MOVr : ARM::tMOVgpr2gpr;
TmpInst.setOpcode(Opc);
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));

4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -333,10 +333,6 @@ def cpinst_operand : Operand<i32> {
let PrintMethod = "printCPInstOperand";
}
def jt2block_operand : Operand<i32> {
let PrintMethod = "printJT2BlockOperand";
}
// Local PC labels.
def pclabel : Operand<i32> {
let PrintMethod = "printPCLabel";

84
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -21,11 +21,6 @@ def it_mask : Operand<i32> {
let PrintMethod = "printThumbITMask";
}
// Table branch address
def tb_addrmode : Operand<i32> {
let PrintMethod = "printTBAddrMode";
}
// Shifted operands. No register controlled shifts for Thumb2.
// Note: We do not support rrx shifted operands yet.
def t2_so_reg : Operand<i32>, // reg imm
@ -2933,59 +2928,40 @@ def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
let isNotDuplicable = 1, isIndirectBranch = 1,
isCodeGenOnly = 1 in { // $id doesn't exist in asmstring, should be lowered.
def t2BR_JT :
T2JTI<(outs),
(ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
IIC_Br, "mov\tpc, $target$jt",
[(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0100100;
let Inst{19-16} = 0b1111;
let Inst{14-12} = 0b000;
let Inst{11-8} = 0b1111; // Rd = pc
let Inst{7-4} = 0b0000;
}
tPseudoInst<(outs),
(ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
SizeSpecial, IIC_Br,// "mov\tpc, $target$jt",
[(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
// FIXME: Add a non-pc based case that can be predicated.
let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
def t2TBB_JT :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
IIC_Br, "tbb\t$index$jt", []> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001101;
let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
let Inst{15-8} = 0b11110000;
let Inst{7-4} = 0b0000; // B form
def t2TBB_JT : tPseudoInst<(outs),
(ins GPR:$index, i32imm:$jt, i32imm:$id),
SizeSpecial, IIC_Br, []>;
def t2TBH_JT : tPseudoInst<(outs),
(ins GPR:$index, i32imm:$jt, i32imm:$id),
SizeSpecial, IIC_Br, []>;
def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
"tbb", "\t[$Rn, $Rm]", []> {
bits<4> Rn;
bits<4> Rm;
let Inst{27-20} = 0b10001101;
let Inst{19-16} = Rn;
let Inst{15-5} = 0b11110000000;
let Inst{4} = 0; // B form
let Inst{3-0} = Rm;
}
let isCodeGenOnly = 1 in // $id doesn't exist in asm string, should be lowered.
def t2TBH_JT :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
IIC_Br, "tbh\t$index$jt", []> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001101;
let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
let Inst{15-8} = 0b11110000;
let Inst{7-4} = 0b0001; // H form
}
// Generic versions of the above two instructions, for disassembly only
def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
"tbb", "\t[$a, $b]", []>{
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001101;
let Inst{15-8} = 0b11110000;
let Inst{7-4} = 0b0000; // B form
}
def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br,
"tbh", "\t[$a, $b, lsl #1]", []> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001101;
let Inst{15-8} = 0b11110000;
let Inst{7-4} = 0b0001; // H form
def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
"tbh", "\t[$Rn, $Rm, lsl #1]", []> {
bits<4> Rn;
bits<4> Rm;
let Inst{27-20} = 0b10001101;
let Inst{19-16} = Rn;
let Inst{15-5} = 0b11110000000;
let Inst{4} = 1; // H form
let Inst{3-0} = Rm;
}
} // isNotDuplicable, isIndirectBranch

67
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -789,7 +789,6 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
}
// Misc. Branch Instructions.
// BR_JTadd, BR_JTr, BR_JTm
// BLXr9, BXr9
// BRIND, BX_RET
static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
@ -816,72 +815,6 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return true;
}
// BR_JTadd is an ADD with Rd = PC, (Rn, Rm) as the target and index regs.
if (Opcode == ARM::BR_JTadd) {
// InOperandList with GPR:$target and GPR:$idx regs.
assert(NumOps == 4 && "Expect 4 operands");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
// Fill in the two remaining imm operands to signify build completion.
MI.addOperand(MCOperand::CreateImm(0));
MI.addOperand(MCOperand::CreateImm(0));
OpIdx = 4;
return true;
}
// BR_JTr is a MOV with Rd = PC, and Rm as the source register.
if (Opcode == ARM::BR_JTr) {
// InOperandList with GPR::$target reg.
assert(NumOps == 3 && "Expect 3 operands");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
// Fill in the two remaining imm operands to signify build completion.
MI.addOperand(MCOperand::CreateImm(0));
MI.addOperand(MCOperand::CreateImm(0));
OpIdx = 3;
return true;
}
// BR_JTm is an LDR with Rt = PC.
if (Opcode == ARM::BR_JTm) {
// This is the reg/reg form, with base reg followed by +/- reg shop imm.
// See also ARMAddressingModes.h (Addressing Mode #2).
assert(NumOps == 5 && getIBit(insn) == 1 && "Expect 5 operands && I-bit=1");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
// Disassemble the offset reg (Rm), shift type, and immediate shift length.
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
// Inst{6-5} encodes the shift opcode.
ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
// Inst{11-7} encodes the imm5 shift amount.
unsigned ShImm = slice(insn, 11, 7);
// A8.4.1. Possible rrx or shift amount of 32...
getImmShiftSE(ShOp, ShImm);
MI.addOperand(MCOperand::CreateImm(
ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
// Fill in the two remaining imm operands to signify build completion.
MI.addOperand(MCOperand::CreateImm(0));
MI.addOperand(MCOperand::CreateImm(0));
OpIdx = 5;
return true;
}
return false;
}

10
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -1248,13 +1248,7 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode,
return true;
}
// PC-based defined for Codegen, which do not get decoded by design:
//
// t2TBB, t2TBH: Rm immDontCare immDontCare
//
// Generic version defined for disassembly:
//
// t2TBBgen, t2TBHgen: Rn Rm Pred-Imm Pred-CCR
// t2TBB, t2TBH: Rn Rm Pred-Imm Pred-CCR
static bool DisassembleThumb2TB(MCInst &MI, unsigned Opcode,
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@ -2125,7 +2119,7 @@ static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
return DisassembleThumb2LdStDual(MI, Opcode, insn, NumOps, NumOpsAdded,
B);
}
if (Opcode == ARM::t2TBBgen || Opcode == ARM::t2TBHgen) {
if (Opcode == ARM::t2TBB || Opcode == ARM::t2TBH) {
// Table branch.
return DisassembleThumb2TB(MI, Opcode, insn, NumOps, NumOpsAdded, B);
}

8
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -528,14 +528,6 @@ void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
O << "]";
}
void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
if (MI->getOpcode() == ARM::t2TBH_JT)
O << ", lsl #1";
O << ']';
}
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
// register with shift forms.
// REG 0 0 - e.g. R5

4
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@ -94,10 +94,6 @@ public:
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
// The jump table instructions have custom handling in ARMAsmPrinter
// to output the jump table. Nothing further is necessary here.
void printJT2BlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {}
void printTBAddrMode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

7
utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1718,10 +1718,6 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
if (Name == "t2LDRDpci")
return false;
// Ignore t2TBB, t2TBH and prefer the generic t2TBBgen, t2TBHgen.
if (Name == "t2TBB_JT" || Name == "t2TBH_JT")
return false;
// Resolve conflicts:
//
// tBfar conflicts with tBLr9
@ -1729,7 +1725,6 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
// tPOP_RET/t2LDMIA_RET conflict with tPOP/t2LDM (ditto)
// tMOVCCi conflicts with tMOVi8
// tMOVCCr conflicts with tMOVgpr2gpr
// tBR_JTr conflicts with tBRIND
// tSpill conflicts with tSTRspi
// tLDRcp conflicts with tLDRspi
// tRestore conflicts with tLDRspi
@ -1740,7 +1735,7 @@ bool ARMDecoderEmitter::ARMDEBackend::populateInstruction(
Name == "tCMPzhir" || /* Name == "t2CMNzrr" || Name == "t2CMNzrs" ||
Name == "t2CMNzri" || */ Name == "t2CMPzrr" || Name == "t2CMPzrs" ||
Name == "t2CMPzri" || Name == "tPOP_RET" || Name == "t2LDMIA_RET" ||
Name == "tMOVCCi" || Name == "tMOVCCr" || Name == "tBR_JTr" ||
Name == "tMOVCCi" || Name == "tMOVCCr" ||
Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" ||
Name == "t2LEApcrelJT" || Name == "t2MOVCCi16")
return false;