From 5cbba0167165c61deb8f3223143643083013f046 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Sat, 13 Aug 2011 20:31:45 +0000 Subject: [PATCH] Fix PR 10635. When generating integer constants, the constant element type may be illegal, even if the requested vector type is legal. Testcase is one of the disabled ARM tests in the vector-select patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137562 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 8b353a28b6b..ab6af1b4d17 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -928,6 +928,13 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) { assert(Val.getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"); + // In some cases the vector type is legal but the element type is illegal. + // In this case, promote the inserted value. The type does not need to match + // the vector element type. Any extra bits introduced will be + // truncated away. + if (VT.isVector()) + EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT); + unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);