diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 46a10f0e76a..0b4a19bc3be 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -232,7 +232,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
     case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
     case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
     case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
-    case X86II::TwoArgFP:   handleTwoArgFP(I); break;
+    case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
     case X86II::CompareFP:  handleCompareFP(I); break;
     case X86II::CondMovFP:  handleCondMovFP(I); break;
     case X86II::SpecialFP:  handleSpecialFP(I); break;
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index ddc730d9593..1a6e60ad5be 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -525,12 +525,8 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 
     // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
     if (ContainsFPCode) {
-      const TargetInstrDescriptor &II= TM.getInstrInfo()->get(X86::FP_REG_KILL);
-      MachineInstrBuilder MIB =
-        BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
-      for (const unsigned *ImplicitDefs = II.ImplicitDefs;
-           *ImplicitDefs; ++ImplicitDefs)
-        MIB = MIB.addReg(*ImplicitDefs, true, true);
+      BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0).
+        addImplicitDefsUses();
       ++NumFPKill;
     }
   }
@@ -541,7 +537,8 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
                                              MachineFrameInfo *MFI) {
   if (Subtarget->isTargetCygwin())
-    BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
+    BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main").
+      addImplicitDefsUses();
 
   // Switch the FPU to 64-bit precision mode for better compatibility and speed.
   int CWFrameIdx = MFI->CreateStackObject(2, 2);
@@ -952,7 +949,8 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
     // type of register here.
     GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
     BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
-    BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
+    BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg).
+      addImplicitDefsUses();
   }
   return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
 }
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 80fe1be685b..45ee23f8035 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5076,7 +5076,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
     MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
     unsigned Opc = 
       X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
-    BuildMI(BB, Opc, 1).addMBB(sinkMBB);
+    BuildMI(BB, Opc, 1).addMBB(sinkMBB).addImplicitDefsUses();
     MachineFunction *F = BB->getParent();
     F->getBasicBlockList().insert(It, copy0MBB);
     F->getBasicBlockList().insert(It, sinkMBB);