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R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()
This fixes a crash with GNOME settings manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -90,6 +90,7 @@ bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
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bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
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bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
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return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
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return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
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getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
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@ -222,3 +222,49 @@ declare float @llvm.pow.f32(float, float) #4
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; Function Attrs: nounwind readnone
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #1
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declare i32 @llvm.SI.packf16(float, float) #1
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; This checks for a bug in the FixSGPRCopies pass where VReg96
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; registers were being identified as an SGPR regclass which was causing
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; an assertion failure.
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; CHECK-LABEL: @sample_v3
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; CHECK: IMAGE_SAMPLE
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; CHECK: IMAGE_SAMPLE
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; CHECK: EXP
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; CHECK: S_ENDPGM
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define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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entry:
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%21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
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%22 = load <16 x i8> addrspace(2)* %21, !tbaa !2
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%23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
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%24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
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%25 = load <32 x i8> addrspace(2)* %24, !tbaa !2
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%26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
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%27 = load <16 x i8> addrspace(2)* %26, !tbaa !2
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%28 = fcmp oeq float %23, 0.0
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br i1 %28, label %if, label %else
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if:
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%val.if = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 0, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
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%val.if.0 = extractelement <4 x float> %val.if, i32 0
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%val.if.1 = extractelement <4 x float> %val.if, i32 1
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%val.if.2 = extractelement <4 x float> %val.if, i32 2
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br label %endif
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else:
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%val.else = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 1, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2)
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%val.else.0 = extractelement <4 x float> %val.else, i32 0
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%val.else.1 = extractelement <4 x float> %val.else, i32 1
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%val.else.2 = extractelement <4 x float> %val.else, i32 2
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br label %endif
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endif:
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%val.0 = phi float [%val.if.0, %if], [%val.else.0, %else]
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%val.1 = phi float [%val.if.1, %if], [%val.else.1, %else]
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%val.2 = phi float [%val.if.2, %if], [%val.else.2, %else]
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.0)
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ret void
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}
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!2 = metadata !{metadata !"const", null, i32 1}
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