From 5ce227e7878c5f881214180909c5f868e47a37aa Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 22 Apr 2015 16:43:53 +0000 Subject: [PATCH] [Hexagon] Overhaul of stack object allocation - Use static allocation for aligned stack objects. - Simplify dynamic stack object allocation. - Simplify elimination of frame-indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235521 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonFrameLowering.cpp | 1153 ++++++++++++++--- lib/Target/Hexagon/HexagonFrameLowering.h | 41 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 49 +- lib/Target/Hexagon/HexagonISelLowering.cpp | 152 +-- lib/Target/Hexagon/HexagonISelLowering.h | 2 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 6 + lib/Target/Hexagon/HexagonInstrInfo.td | 42 +- .../Hexagon/HexagonMachineFunctionInfo.h | 9 +- lib/Target/Hexagon/HexagonRegisterInfo.cpp | 269 ++-- lib/Target/Hexagon/HexagonRegisterInfo.h | 32 +- 10 files changed, 1318 insertions(+), 437 deletions(-) diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index 65d689b4d80..e61dbbd19db 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -8,6 +8,8 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "hexagon-pei" + #include "HexagonFrameLowering.h" #include "Hexagon.h" #include "HexagonInstrInfo.h" @@ -30,10 +32,95 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +// Hexagon stack frame layout as defined by the ABI: +// +// Incoming arguments +// passed via stack +// | +// | +// SP during function's FP during function's | +// +-- runtime (top of stack) runtime (bottom) --+ | +// | | | +// --++---------------------+------------------+-----------------++-+------- +// | parameter area for | variable-size | fixed-size |LR| arg +// | called functions | local objects | local objects |FP| +// --+----------------------+------------------+-----------------+--+------- +// <- size known -> <- size unknown -> <- size known -> +// +// Low address High address +// +// <--- stack growth +// +// +// - In any circumstances, the outgoing function arguments are always accessi- +// ble using the SP, and the incoming arguments are accessible using the FP. +// - If the local objects are not aligned, they can always be accessed using +// the FP. +// - If there are no variable-sized objects, the local objects can always be +// accessed using the SP, regardless whether they are aligned or not. (The +// alignment padding will be at the bottom of the stack (highest address), +// and so the offset with respect to the SP will be known at the compile- +// -time.) +// +// The only complication occurs if there are both, local aligned objects, and +// dynamically allocated (variable-sized) objects. The alignment pad will be +// placed between the FP and the local objects, thus preventing the use of the +// FP to access the local objects. At the same time, the variable-sized objects +// will be between the SP and the local objects, thus introducing an unknown +// distance from the SP to the locals. +// +// To avoid this problem, a new register is created that holds the aligned +// address of the bottom of the stack, referred in the sources as AP (aligned +// pointer). The AP will be equal to "FP-p", where "p" is the smallest pad +// that aligns AP to the required boundary (a maximum of the alignments of +// all stack objects, fixed- and variable-sized). All local objects[1] will +// then use AP as the base pointer. +// [1] The exception is with "fixed" stack objects. "Fixed" stack objects get +// their name from being allocated at fixed locations on the stack, relative +// to the FP. In the presence of dynamic allocation and local alignment, such +// objects can only be accessed through the FP. +// +// Illustration of the AP: +// FP --+ +// | +// ---------------+---------------------+-----+-----------------------++-+-- +// Rest of the | Local stack objects | Pad | Fixed stack objects |LR| +// stack frame | (aligned) | | (CSR, spills, etc.) |FP| +// ---------------+---------------------+-----+-----------------+-----+--+-- +// |<-- Multiple of the -->| +// stack alignment +-- AP +// +// The AP is set up at the beginning of the function. Since it is not a dedi- +// cated (reserved) register, it needs to be kept live throughout the function +// to be available as the base register for local object accesses. +// Normally, an address of a stack objects is obtained by a pseudo-instruction +// TFR_FI. To access local objects with the AP register present, a different +// pseudo-instruction needs to be used: TFR_FIA. The TFR_FIA takes one extra +// argument compared to TFR_FI: the first input register is the AP register. +// This keeps the register live between its definition and its uses. + +// The AP register is originally set up using pseudo-instruction ALIGNA: +// AP = ALIGNA A +// where +// A - required stack alignment +// The alignment value must be the maximum of all alignments required by +// any stack object. + +// The dynamic allocation uses a pseudo-instruction ALLOCA: +// Rd = ALLOCA Rs, A +// where +// Rd - address of the allocated space +// Rs - minimum size (the actual allocated can be larger to accommodate +// alignment) +// A - required alignment + + using namespace llvm; static cl::opt DisableDeallocRet( @@ -41,99 +128,234 @@ static cl::opt DisableDeallocRet( cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target")); -/// determineFrameLayout - Determine the size of the frame and maximum call -/// frame size. -void HexagonFrameLowering::determineFrameLayout(MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); +static cl::opt +DisableProEpilogCodeMerge("disable-hexagon-prolog-epilog-code-merge", + cl::Hidden, cl::desc("Disable prolog/epilog code merge"), cl::init(false), + cl::ZeroOrMore); - // Get the number of bytes to allocate from the FrameInfo. - unsigned FrameSize = MFI->getStackSize(); +static cl::opt +NumberScavengerSlots("number-scavenger-slots", + cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), + cl::ZeroOrMore); - // Get the alignments provided by the target. - unsigned TargetAlign = - MF.getSubtarget().getFrameLowering()->getStackAlignment(); - // Get the maximum call frame size of all the calls. - unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); +static cl::opt +SpillFuncThreshold("spill-func-threshold", + cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), + cl::init(6), cl::ZeroOrMore); - // If we have dynamic alloca then maxCallFrameSize needs to be aligned so - // that allocations will be aligned. - if (MFI->hasVarSizedObjects()) - maxCallFrameSize = RoundUpToAlignment(maxCallFrameSize, TargetAlign); +static cl::opt +SpillFuncThresholdOs("spill-func-threshold-Os", + cl::Hidden, cl::desc("Specify Os spill func threshold"), + cl::init(1), cl::ZeroOrMore); - // Update maximum call frame size. - MFI->setMaxCallFrameSize(maxCallFrameSize); +/// Map a register pair Reg to the subregister that has the greater "number", +/// i.e. D3 (aka R7:6) will be mapped to R7, etc. +static unsigned getMax32BitSubRegister(unsigned Reg, + const TargetRegisterInfo *TRI, + bool hireg = true) { + if (Reg < Hexagon::D0 || Reg > Hexagon::D15) + return Reg; - // Include call frame size in total. - FrameSize += maxCallFrameSize; + unsigned RegNo = 0; - // Make sure the frame is aligned. - FrameSize = RoundUpToAlignment(FrameSize, TargetAlign); + for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) + if (hireg) { + if (*SubRegs > RegNo) + RegNo = *SubRegs; + } else { + if (!RegNo || *SubRegs < RegNo) + RegNo = *SubRegs; + } - // Update frame info. - MFI->setStackSize(FrameSize); + return RegNo; } +/// Returns the biggest callee saved register in the vector. +static unsigned getMaxCalleeSavedReg(const std::vector &CSI, + const TargetRegisterInfo *TRI) { + assert(Hexagon::R1 > 0 && + "Assume physical registers are encoded as positive integers"); + if (CSI.empty()) + return 0; + + unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI); + for (unsigned I = 1, E = CSI.size(); I < E; ++I) { + unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI); + if (Reg > Max) + Max = Reg; + } + + return Max; +} void HexagonFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineModuleInfo &MMI = MF.getMMI(); MachineBasicBlock::iterator MBBI = MBB.begin(); - const HexagonRegisterInfo *QRI = - MF.getSubtarget().getRegisterInfo(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - determineFrameLayout(MF); + auto &HTM = static_cast(MF.getTarget()); + auto &HST = static_cast(MF.getSubtarget()); + auto &HII = *HST.getInstrInfo(); + auto &HRI = *HST.getRegisterInfo(); + DebugLoc dl; + + unsigned MaxAlign = std::max(MFI->getMaxAlignment(), getStackAlignment()); + + // Calculate the total stack frame size. + // Get the number of bytes to allocate from the FrameInfo. + unsigned FrameSize = MFI->getStackSize(); + // Round up the max call frame size to the max alignment on the stack. + unsigned MaxCFA = RoundUpToAlignment(MFI->getMaxCallFrameSize(), MaxAlign); + MFI->setMaxCallFrameSize(MaxCFA); + + FrameSize = MaxCFA + RoundUpToAlignment(FrameSize, MaxAlign); + MFI->setStackSize(FrameSize); + + bool AlignStack = (MaxAlign > 8); + + // Check if frame moves are needed for EH. + bool needsFrameMoves = MMI.hasDebugInfo() || + MF.getFunction()->needsUnwindTableEntry(); // Get the number of bytes to allocate from the FrameInfo. - int NumBytes = (int) MFI->getStackSize(); - - // LLVM expects allocframe not to be the first instruction in the - // basic block. + unsigned NumBytes = MFI->getStackSize(); + unsigned SP = HRI.getStackRegister(); + unsigned MaxCF = MFI->getMaxCallFrameSize(); MachineBasicBlock::iterator InsertPt = MBB.begin(); - // - // ALLOCA adjust regs. Iterate over ADJDYNALLOC nodes and change the offset. - // - HexagonMachineFunctionInfo *FuncInfo = - MF.getInfo(); - const std::vector& AdjustRegs = - FuncInfo->getAllocaAdjustInsts(); - for (std::vector::const_iterator i = AdjustRegs.begin(), - e = AdjustRegs.end(); - i != e; ++i) { - MachineInstr* MI = *i; - assert((MI->getOpcode() == Hexagon::ADJDYNALLOC) && - "Expected adjust alloca node"); + auto *FuncInfo = MF.getInfo(); + auto &AdjustRegs = FuncInfo->getAllocaAdjustInsts(); - MachineOperand& MO = MI->getOperand(2); - assert(MO.isImm() && "Expected immediate"); - MO.setImm(MFI->getMaxCallFrameSize()); + for (auto MI : AdjustRegs) { + assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca"); + expandAlloca(MI, HII, SP, MaxCF); + MI->eraseFromParent(); } // - // Only insert ALLOCFRAME if we need to. + // Only insert ALLOCFRAME if we need to or at -O0 for the debugger. Think + // that this shouldn't be required, but doing so now because gcc does and + // gdb can't break at the start of the function without it. Will remove if + // this turns out to be a gdb bug. // - if (hasFP(MF)) { - // Check for overflow. - // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used? - const int ALLOCFRAME_MAX = 16384; - const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + bool NoOpt = (HTM.getOptLevel() == CodeGenOpt::None); + if (!NoOpt && !FuncInfo->hasClobberLR() && !hasFP(MF)) + return; - if (NumBytes >= ALLOCFRAME_MAX) { - // Emit allocframe(#0). - BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::S2_allocframe)).addImm(0); + // Check for overflow. + // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used? + const unsigned int ALLOCFRAME_MAX = 16384; - // Subtract offset from frame pointer. - BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real), - HEXAGON_RESERVED_REG_1).addImm(NumBytes); - BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::A2_sub), - QRI->getStackRegister()). - addReg(QRI->getStackRegister()). - addReg(HEXAGON_RESERVED_REG_1); - } else { - BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::S2_allocframe)).addImm(NumBytes); - } + // Create a dummy memory operand to avoid allocframe from being treated as + // a volatile memory reference. + MachineMemOperand *MMO = + MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore, + 4, 4); + + if (NumBytes >= ALLOCFRAME_MAX) { + // Emit allocframe(#0). + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe)) + .addImm(0) + .addMemOperand(MMO); + + // Subtract offset from frame pointer. + // We use a caller-saved non-parameter register for that. + unsigned CallerSavedReg = HRI.getFirstCallerSavedNonParamReg(); + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::CONST32_Int_Real), + CallerSavedReg).addImm(NumBytes); + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_sub), SP). + addReg(SP). + addReg(CallerSavedReg); + } else { + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe)) + .addImm(NumBytes) + .addMemOperand(MMO); } + + if (AlignStack) { + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP) + .addReg(SP) + .addImm(-int64_t(MaxAlign)); + } + + if (needsFrameMoves) { + std::vector Instructions = MMI.getFrameInstructions(); + MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); + + // Advance CFA. DW_CFA_def_cfa + unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true); + unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true); + + // CFA = FP + 8 + unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa( + FrameLabel, DwFPReg, -8)); + BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + + // R31 (return addr) = CFA - #4 + CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( + FrameLabel, DwRAReg, -4)); + BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + + // R30 (frame ptr) = CFA - #8) + CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( + FrameLabel, DwFPReg, -8)); + BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + + unsigned int regsToMove[] = { + Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2, + Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18, + Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22, + Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26, + Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9, Hexagon::D10, + Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::NoRegister + }; + + const std::vector &CSI = MFI->getCalleeSavedInfo(); + + for (unsigned i = 0; regsToMove[i] != Hexagon::NoRegister; ++i) { + for (unsigned I = 0, E = CSI.size(); I < E; ++I) { + if (CSI[I].getReg() == regsToMove[i]) { + // Subtract 8 to make room for R30 and R31, which are added above. + int64_t Offset = getFrameIndexOffset(MF, CSI[I].getFrameIdx()) - 8; + + if (regsToMove[i] < Hexagon::D0 || regsToMove[i] > Hexagon::D15) { + unsigned DwarfReg = HRI.getDwarfRegNum(regsToMove[i], true); + unsigned CFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(FrameLabel, + DwarfReg, Offset)); + BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + } else { + // Split the double regs into subregs, and generate appropriate + // cfi_offsets. + // The only reason, we are split double regs is, llvm-mc does not + // understand paired registers for cfi_offset. + // Eg .cfi_offset r1:0, -64 + unsigned HiReg = getMax32BitSubRegister(regsToMove[i], &HRI); + unsigned LoReg = getMax32BitSubRegister(regsToMove[i], &HRI, false); + unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); + unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); + unsigned HiCFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(FrameLabel, + HiDwarfReg, Offset+4)); + BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(HiCFIIndex); + unsigned LoCFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(FrameLabel, + LoDwarfReg, Offset)); + BuildMI(MBB, MBBI, dl, HII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(LoCFIIndex); + } + break; + } + } // for CSI.size() + } // for regsToMove + } // needsFrameMoves } + // Returns true if MBB has a machine instructions that indicates a tail call // in the block. bool HexagonFrameLowering::hasTailCall(MachineBasicBlock &MBB) const { @@ -144,59 +366,62 @@ bool HexagonFrameLowering::hasTailCall(MachineBasicBlock &MBB) const { } void HexagonFrameLowering::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = std::prev(MBB.end()); - DebugLoc dl = MBBI->getDebugLoc(); + MachineBasicBlock &MBB) const { // // Only insert deallocframe if we need to. Also at -O0. See comment // in emitPrologue above. // - if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) { - MachineBasicBlock::iterator MBBI = std::prev(MBB.end()); - MachineBasicBlock::iterator MBBI_end = MBB.end(); + if (!hasFP(MF) && MF.getTarget().getOptLevel() != CodeGenOpt::None) + return; - const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); - // Handle EH_RETURN. - if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) { - assert(MBBI->getOperand(0).isReg() && "Offset should be in register!"); - BuildMI(MBB, MBBI, dl, TII.get(Hexagon::L2_deallocframe)); - BuildMI(MBB, MBBI, dl, TII.get(Hexagon::A2_add), - Hexagon::R29).addReg(Hexagon::R29).addReg(Hexagon::R28); + auto &HST = static_cast(MF.getSubtarget()); + auto &HII = *HST.getInstrInfo(); + + MachineBasicBlock::iterator MBBI = std::prev(MBB.end()); + MachineBasicBlock::iterator MBBI_end = MBB.end(); + DebugLoc dl = MBBI->getDebugLoc(); + + // Handle EH_RETURN. + if (MBBI->getOpcode() == Hexagon::EH_RETURN_JMPR) { + MachineOperand &OffsetReg = MBBI->getOperand(0); + assert(OffsetReg.isReg() && "Offset should be in register!"); + BuildMI(MBB, MBBI, dl, HII.get(Hexagon::L2_deallocframe)); + BuildMI(MBB, MBBI, dl, HII.get(Hexagon::A2_add), + Hexagon::R29).addReg(Hexagon::R29).addReg(Hexagon::R28); + return; + } + // Replace 'jumpr r31' instruction with dealloc_return for V4 and higher + // versions. + if (MBBI->getOpcode() == Hexagon::JMPret && !DisableDeallocRet) { + // Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC + // instruction if we encounter it. + MachineBasicBlock::iterator BeforeJMPR = + MBB.begin() == MBBI ? MBBI : std::prev(MBBI); + if (BeforeJMPR != MBBI && + BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) { + // Remove the JMPR node. + MBB.erase(MBBI); return; } - // Replace 'jumpr r31' instruction with dealloc_return for V4 and higher - // versions. - if (MBBI->getOpcode() == Hexagon::JMPret && !DisableDeallocRet) { - // Check for RESTORE_DEALLOC_RET_JMP_V4 call. Don't emit an extra DEALLOC - // instruction if we encounter it. - MachineBasicBlock::iterator BeforeJMPR = - MBB.begin() == MBBI ? MBBI : std::prev(MBBI); - if (BeforeJMPR != MBBI && - BeforeJMPR->getOpcode() == Hexagon::RESTORE_DEALLOC_RET_JMP_V4) { - // Remove the JMPR node. - MBB.erase(MBBI); - return; - } - // Add dealloc_return. - MachineInstrBuilder MIB = - BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::L4_return)); - // Transfer the function live-out registers. - MIB->copyImplicitOps(*MBB.getParent(), &*MBBI); - // Remove the JUMPR node. - MBB.erase(MBBI); - } else { // Add deallocframe for V2 and V3, and V4 tail calls. - // Check for RESTORE_DEALLOC_BEFORE_TAILCALL_V4. We don't need an extra - // DEALLOCFRAME instruction after it. - MachineBasicBlock::iterator Term = MBB.getFirstTerminator(); - MachineBasicBlock::iterator I = - Term == MBB.begin() ? MBB.end() : std::prev(Term); - if (I != MBB.end() && - I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4) - return; + // Add dealloc_return. + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI_end, dl, HII.get(Hexagon::L4_return)); + // Transfer the function live-out registers. + MIB->copyImplicitOps(*MBB.getParent(), &*MBBI); + // Remove the JUMPR node. + MBB.erase(MBBI); + } else { // Add deallocframe for tail calls. + // Check for RESTORE_DEALLOC_BEFORE_TAILCALL_V4. We don't need an extra + // L2_deallocframe instruction after it. + MachineBasicBlock::iterator Term = MBB.getFirstTerminator(); + MachineBasicBlock::iterator I = + Term == MBB.begin() ? MBB.end() : std::prev(Term); + if (I != MBB.end() && + I->getOpcode() == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4) + return; - BuildMI(MBB, MBBI, dl, TII.get(Hexagon::L2_deallocframe)); - } + BuildMI(MBB, MBBI, dl, HII.get(Hexagon::L2_deallocframe)); } } @@ -208,14 +433,99 @@ bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const { FuncInfo->hasClobberLR() ); } -static inline -unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { - MCSuperRegIterator SRI(Reg, TRI); - assert(SRI.isValid() && "Expected a superreg"); - unsigned SuperReg = *SRI; - ++SRI; - assert(!SRI.isValid() && "Expected exactly one superreg"); - return SuperReg; +enum SpillKind { + SK_ToMem, + SK_FromMem, + SK_FromMemTailcall +}; + +static const char * +getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType) { + const char * V4SpillToMemoryFunctions[] = { + "__save_r16_through_r17", + "__save_r16_through_r19", + "__save_r16_through_r21", + "__save_r16_through_r23", + "__save_r16_through_r25", + "__save_r16_through_r27" }; + + const char * V4SpillFromMemoryFunctions[] = { + "__restore_r16_through_r17_and_deallocframe", + "__restore_r16_through_r19_and_deallocframe", + "__restore_r16_through_r21_and_deallocframe", + "__restore_r16_through_r23_and_deallocframe", + "__restore_r16_through_r25_and_deallocframe", + "__restore_r16_through_r27_and_deallocframe" }; + + const char * V4SpillFromMemoryTailcallFunctions[] = { + "__restore_r16_through_r17_and_deallocframe_before_tailcall", + "__restore_r16_through_r19_and_deallocframe_before_tailcall", + "__restore_r16_through_r21_and_deallocframe_before_tailcall", + "__restore_r16_through_r23_and_deallocframe_before_tailcall", + "__restore_r16_through_r25_and_deallocframe_before_tailcall", + "__restore_r16_through_r27_and_deallocframe_before_tailcall" + }; + + const char **SpillFunc = nullptr; + + switch(SpillType) { + case SK_ToMem: + SpillFunc = V4SpillToMemoryFunctions; + break; + case SK_FromMem: + SpillFunc = V4SpillFromMemoryFunctions; + break; + case SK_FromMemTailcall: + SpillFunc = V4SpillFromMemoryTailcallFunctions; + break; + } + assert(SpillFunc && "Unknown spill kind"); + + // Spill all callee-saved registers up to the highest register used. + switch (MaxReg) { + case Hexagon::R17: + return SpillFunc[0]; + case Hexagon::R19: + return SpillFunc[1]; + case Hexagon::R21: + return SpillFunc[2]; + case Hexagon::R23: + return SpillFunc[3]; + case Hexagon::R25: + return SpillFunc[4]; + case Hexagon::R27: + return SpillFunc[5]; + default: + assert(false && "Unhandled maximum callee save register"); + break; + } + return 0; +} + +/// Adds all callee-saved registers up to MaxReg to the instruction. +static void addCalleeSaveRegistersAsImpOperand(MachineInstr *Inst, + unsigned MaxReg, bool IsDef) { + // Add the callee-saved registers as implicit uses. + for (unsigned R = Hexagon::R16; R <= MaxReg; ++R) { + MachineOperand ImpUse = MachineOperand::CreateReg(R, IsDef, true); + Inst->addOperand(ImpUse); + } +} + +/// Returns true if we have V4 operations, optimization level is equal to +/// O2 or Os and exception handling is not required. +static bool shouldOptimizeForSize(MachineFunction &MF) { + if (MF.getInfo()->hasEHReturn()) + return false; + + if (MF.getTarget().getOptLevel() == CodeGenOpt::Default) /* -O2 or -Os */ + return true; + + const Function *F = MF.getFunction(); + if (F->hasFnAttribute(Attribute::MinSize)) + return true; + + return F->hasFnAttribute(Attribute::OptimizeForSize); } bool @@ -226,47 +536,62 @@ HexagonFrameLowering::spillCalleeSavedRegisters( const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + const HexagonRegisterInfo *HRI = + static_cast(TRI); if (CSI.empty()) { return false; } - // We can only schedule double loads if we spill contiguous callee-saved regs - // For instance, we cannot scheduled double-word loads if we spill r24, - // r26, and r27. - // Hexagon_TODO: We can try to double-word align odd registers for -O2 and - // above. - bool ContiguousRegs = true; + // Check whether we should emit a function call to spill the registers. + bool ShouldOptimizeForSize = shouldOptimizeForSize(*MF); + + if (ShouldOptimizeForSize && !DisableProEpilogCodeMerge) { + // We have different cut offs when we use callee saved stubs at -Os. + bool HasOptimizeForSizeAttr = MF->getFunction()->getAttributes() + .hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); + unsigned CalleeSavedStubCutOff = HasOptimizeForSizeAttr ? + SpillFuncThresholdOs : SpillFuncThreshold; + + // Use a function call if we have to spill registers. + if (CSI.size() > CalleeSavedStubCutOff) { + unsigned MaxReg = getMaxCalleeSavedReg(CSI, TRI); + const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem); + // Call spill function. + DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); + MachineInstr *SaveRegsCall = + BuildMI(MBB, MI, DL, TII.get(Hexagon::SAVE_REGISTERS_CALL_V4)) + .addExternalSymbol(SpillFun); + // Add callee-saved registers as use. + addCalleeSaveRegistersAsImpOperand(SaveRegsCall, MaxReg, false); + // Add live in registers. + for (unsigned I = 0; I < CSI.size(); ++I) + MBB.addLiveIn(CSI[I].getReg()); + return true; + } + } for (unsigned i = 0; i < CSI.size(); ++i) { unsigned Reg = CSI[i].getReg(); + // Add live in registers. We treat eh_return callee saved register r0 - r3 + // specially. They are not really callee saved registers as they are not + // supposed to be killed. + bool IsEHReturnCalleeSavedReg = HRI->isEHReturnCalleeSaveReg(Reg); - // - // Check if we can use a double-word store. - // - unsigned SuperReg = uniqueSuperReg(Reg, TRI); - bool CanUseDblStore = false; - const TargetRegisterClass* SuperRegClass = nullptr; - - if (ContiguousRegs && (i < CSI.size()-1)) { - unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); - SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); - CanUseDblStore = (SuperRegNext == SuperReg); - } - - - if (CanUseDblStore) { - TII.storeRegToStackSlot(MBB, MI, SuperReg, true, - CSI[i+1].getFrameIdx(), SuperRegClass, TRI); - MBB.addLiveIn(SuperReg); - ++i; + if (HRI->isCalleeSaveReg(Reg)) { + int FrameIdx = CSI[i].getFrameIdx(); + const TargetRegisterClass *RegClass = + TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, !IsEHReturnCalleeSavedReg, + FrameIdx, RegClass, TRI); + if (!IsEHReturnCalleeSavedReg) + MBB.addLiveIn(Reg); } else { - // Cannot use a double-word store. - ContiguousRegs = false; const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RC, - TRI); - MBB.addLiveIn(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, !IsEHReturnCalleeSavedReg, + CSI[i].getFrameIdx(), RC, TRI); + if (!IsEHReturnCalleeSavedReg) + MBB.addLiveIn(Reg); } } return true; @@ -286,40 +611,72 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters( return false; } - // We can only schedule double loads if we spill contiguous callee-saved regs - // For instance, we cannot scheduled double-word loads if we spill r24, - // r26, and r27. - // Hexagon_TODO: We can try to double-word align odd registers for -O2 and - // above. - bool ContiguousRegs = true; + // Check whether we should emit a function call to spill the registers. + bool ShouldOptimizeForSize = shouldOptimizeForSize(*MF); + + if (ShouldOptimizeForSize && !DisableProEpilogCodeMerge) { + // We have different cut offs when we use callee saved stubs at -Os. + bool HasOptimizeForSizeAttr = MF->getFunction()->getAttributes() + .hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); + unsigned CalleeSavedStubCutOff = HasOptimizeForSizeAttr ? + (SpillFuncThresholdOs - 1) : SpillFuncThreshold; + + // Use a function call if we have to spill registers. + if (CSI.size() > CalleeSavedStubCutOff) { + bool IsTailCallBB = hasTailCall(MBB); + unsigned MaxReg = getMaxCalleeSavedReg(CSI, TRI); + const char *SpillFun = + getSpillFunctionFor(MaxReg, IsTailCallBB ? + SK_FromMemTailcall : SK_FromMem); + + // Call spill function. + DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc(); + MachineInstr *DeallocCall = nullptr; + + if (IsTailCallBB) { + DeallocCall = BuildMI(MBB, MI, DL, + TII.get(Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4)) + .addExternalSymbol(SpillFun); + } + else { + MachineBasicBlock::iterator JumprInst = std::prev(MBB.end()); + assert(JumprInst->getOpcode() == Hexagon::JMPret); + DeallocCall = + BuildMI(MBB, MI, DL, TII.get(Hexagon::RESTORE_DEALLOC_RET_JMP_V4)) + .addExternalSymbol(SpillFun); + // Transfer the function live-out registers. + DeallocCall->copyImplicitOps(*MBB.getParent(), JumprInst); + } + addCalleeSaveRegistersAsImpOperand(DeallocCall, MaxReg, true); + return true; + } + } + + const HexagonRegisterInfo *HRI = + static_cast(TRI); for (unsigned i = 0; i < CSI.size(); ++i) { unsigned Reg = CSI[i].getReg(); + // Add live in registers. We treat eh_return callee saved register r0 - r3 + // specially. They are not really callee saved registers as they are not + // supposed to be killed. + bool IsEHReturnCalleeSavedReg = HRI->isEHReturnCalleeSaveReg(Reg); - // - // Check if we can use a double-word load. - // - unsigned SuperReg = uniqueSuperReg(Reg, TRI); - const TargetRegisterClass* SuperRegClass = nullptr; - bool CanUseDblLoad = false; - if (ContiguousRegs && (i < CSI.size()-1)) { - unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); - SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); - CanUseDblLoad = (SuperRegNext == SuperReg); - } + if (HRI->isCalleeSaveReg(Reg)) { + int FrameIdx = CSI[i].getFrameIdx(); + const TargetRegisterClass *RegClass = + TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, Reg, FrameIdx, + RegClass, TRI); + if (!IsEHReturnCalleeSavedReg) + MBB.addLiveIn(Reg); - if (CanUseDblLoad) { - TII.loadRegFromStackSlot(MBB, MI, SuperReg, CSI[i+1].getFrameIdx(), - SuperRegClass, TRI); - MBB.addLiveIn(SuperReg); - ++i; } else { - // Cannot use a double-word load. - ContiguousRegs = false; const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI); - MBB.addLiveIn(Reg); + if (!IsEHReturnCalleeSavedReg) + MBB.addLiveIn(Reg); } } return true; @@ -329,14 +686,9 @@ void HexagonFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { MachineInstr &MI = *I; - - if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) { - // Hexagon_TODO: add code - } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) { - // Hexagon_TODO: add code - } else { - llvm_unreachable("Cannot handle this call frame pseudo instruction"); - } + unsigned Opc = MI.getOpcode(); + assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) && + "Cannot handle this call frame pseudo instruction"); MBB.erase(I); } @@ -344,3 +696,442 @@ int HexagonFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { return MF.getFrameInfo()->getObjectOffset(FI); } + +void HexagonFrameLowering::processFunctionBeforeFrameFinalized( + MachineFunction &MF, RegScavenger *RS) const { + // If this function has uses aligned stack and also has variable sized stack + // objects, then we need to map all spill slots to fixed positions, so that + // they can be accessed through FP. Otherwise they would have to be accessed + // via AP, which may not be available at the particular place in the program. + MachineFrameInfo *MFI = MF.getFrameInfo(); + bool HasAlloca = MFI->hasVarSizedObjects(); + bool HasAligna = (MFI->getMaxAlignment() > getStackAlignment()); + + if (!HasAlloca || !HasAligna) + return; + + unsigned LFS = MFI->getLocalFrameSize(); + int Offset = -LFS; + for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { + if (!MFI->isSpillSlotObjectIndex(i) || MFI->isDeadObjectIndex(i)) + continue; + int S = MFI->getObjectSize(i); + LFS += S; + Offset -= S; + MFI->mapLocalFrameObject(i, Offset); + } + + MFI->setLocalFrameSize(LFS); + unsigned A = MFI->getLocalFrameMaxAlign(); + assert(A <= 8 && "Unexpected local frame alignment"); + if (A == 0) + MFI->setLocalFrameMaxAlign(8); + MFI->setUseLocalStackAllocationBlock(true); +} + +/// Returns true if there is no caller saved registers available. +static bool needToReserveScavengingSpillSlots(MachineFunction &MF, + const HexagonRegisterInfo &HRI) { + MachineRegisterInfo &MRI = MF.getRegInfo(); + const uint16_t *CallerSavedRegs = HRI.getCallerSavedRegs(&MF); + // Check for an unused caller-saved register. + for ( ; *CallerSavedRegs; ++CallerSavedRegs) { + unsigned FreeReg = *CallerSavedRegs; + if (MRI.isPhysRegUsed(FreeReg)) + continue; + + // Check aliased register usage. + bool IsCurrentRegUsed = false; + for (MCRegAliasIterator AI(FreeReg, &HRI, false); AI.isValid(); ++AI) + if (MRI.isPhysRegUsed(*AI)) { + IsCurrentRegUsed = true; + break; + } + if (IsCurrentRegUsed) + continue; + + // Neither directly used nor used through an aliased register. + return false; + } + // All caller-saved registers are used. + return true; +} + +/// Marks physical registers as used so that the callee-saved registers are +/// always a multiple of two. +void HexagonFrameLowering:: +adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const { + // We need to pretend that the callee-saved registers are a multiple of two + // because there are only library functions to handle those cases. + // (save_r16_to_17, save_r16_to_r19, ...) + MachineRegisterInfo &MRI = MF.getRegInfo(); + const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); + const uint16_t *CSRegs = TRI.getCalleeSavedRegs(&MF); + + // Compute the smallest and biggest callee-saved register used. + unsigned Biggest = 0; + unsigned Smallest = Hexagon::R31; + unsigned NumUsed = 0; + for (; *CSRegs; ++CSRegs){ + unsigned CurrCSR = *CSRegs; + if (MRI.isPhysRegUsed(CurrCSR)) { + ++NumUsed; + if (CurrCSR >= Biggest) + Biggest = CurrCSR; + if (CurrCSR <= Smallest) + Smallest = CurrCSR; + continue; + } + // Also check alias registers. + for (MCRegAliasIterator AI(CurrCSR, &TRI, false); AI.isValid(); ++AI) { + if (MRI.isPhysRegUsed(*AI)) { + ++NumUsed; + if (CurrCSR >= Biggest) + Biggest = CurrCSR; + if (CurrCSR <= Smallest) + Smallest = CurrCSR; + break; + } + } + } + + // Don't do anything if the number of register used is zero. + if (NumUsed == 0) + return; + + // Ensure that the biggest register is r17, r19, ... + if ((Biggest - Hexagon::R0) % 2 == 0) + ++Biggest; + assert(Smallest != Hexagon::R31 && "Should not happen"); + // Make sure all the physical register are marked as used so that they are + // assigned stack slots. + for (unsigned I = Smallest; I <= Biggest; ++I) + if (!MRI.isPhysRegUsed(I)) + MRI.setPhysRegUsed(I); +} + +/// Replaces the predicate spill code pseudo instructions by valid instructions. +bool HexagonFrameLowering::replacePredRegPseudoSpillCode(MachineFunction &MF) + const { + auto &HST = static_cast(MF.getSubtarget()); + auto &HII = *HST.getInstrInfo(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + bool HasReplacedPseudoInst = false; + // Replace predicate spill pseudo instructions by real code. + // Loop over all of the basic blocks. + for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); + MBBb != MBBe; ++MBBb) { + MachineBasicBlock* MBB = MBBb; + // Traverse the basic block. + MachineBasicBlock::iterator NextII; + for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end(); + MII = NextII) { + MachineInstr *MI = MII; + NextII = std::next(MII); + int Opc = MI->getOpcode(); + if (Opc == Hexagon::STriw_pred) { + HasReplacedPseudoInst = true; + // STriw_pred FI, 0, SrcReg; + unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); + unsigned SrcReg = MI->getOperand(2).getReg(); + bool IsOrigSrcRegKilled = MI->getOperand(2).isKill(); + + assert(MI->getOperand(0).isFI() && "Expect a frame index"); + assert(Hexagon::PredRegsRegClass.contains(SrcReg) && + "Not a predicate register"); + + // Insert transfer to general purpose register. + // VirtReg = C2_tfrpr SrcPredReg + BuildMI(*MBB, MII, MI->getDebugLoc(), HII.get(Hexagon::C2_tfrpr), + VirtReg).addReg(SrcReg, getKillRegState(IsOrigSrcRegKilled)); + + // Change instruction to S2_storeri_io. + // S2_storeri_io FI, 0, VirtReg + MI->setDesc(HII.get(Hexagon::S2_storeri_io)); + MI->getOperand(2).setReg(VirtReg); + MI->getOperand(2).setIsKill(); + + } else if (Opc == Hexagon::LDriw_pred) { + // DstReg = LDriw_pred FI, 0 + MachineOperand &M0 = MI->getOperand(0); + if (M0.isDead()) { + MBB->erase(MII); + continue; + } + + unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); + unsigned DestReg = MI->getOperand(0).getReg(); + + assert(MI->getOperand(1).isFI() && "Expect a frame index"); + assert(Hexagon::PredRegsRegClass.contains(DestReg) && + "Not a predicate register"); + + // Change instruction to L2_loadri_io. + // VirtReg = L2_loadri_io FI, 0 + MI->setDesc(HII.get(Hexagon::L2_loadri_io)); + MI->getOperand(0).setReg(VirtReg); + + // Insert transfer to general purpose register. + // DestReg = C2_tfrrp VirtReg + const MCInstrDesc &D = HII.get(Hexagon::C2_tfrrp); + BuildMI(*MBB, std::next(MII), MI->getDebugLoc(), D, DestReg) + .addReg(VirtReg, getKillRegState(true)); + HasReplacedPseudoInst = true; + } + } + } + return HasReplacedPseudoInst; +} + +void HexagonFrameLowering::processFunctionBeforeCalleeSavedScan( + MachineFunction &MF, RegScavenger* RS) const { + auto &HST = static_cast(MF.getSubtarget()); + auto &HRI = *HST.getRegisterInfo(); + + bool HasEHReturn = MF.getInfo()->hasEHReturn(); + + // If we have a function containing __builtin_eh_return we want to spill and + // restore all callee saved registers. Pretend that they are used. + if (HasEHReturn) { + MachineRegisterInfo &MRI = MF.getRegInfo(); + for (const uint16_t *CSRegs = HRI.getCalleeSavedRegs(&MF); *CSRegs; + ++CSRegs) + if (!MRI.isPhysRegUsed(*CSRegs)) + MRI.setPhysRegUsed(*CSRegs); + } + + const TargetRegisterClass &RC = Hexagon::IntRegsRegClass; + + // Replace predicate register pseudo spill code. + bool HasReplacedPseudoInst = replacePredRegPseudoSpillCode(MF); + + // We need to reserve a a spill slot if scavenging could potentially require + // spilling a scavenged register. + if (HasReplacedPseudoInst && needToReserveScavengingSpillSlots(MF, HRI)) { + MachineFrameInfo *MFI = MF.getFrameInfo(); + for (int i=0; i < NumberScavengerSlots; i++) + RS->addScavengingFrameIndex( + MFI->CreateSpillStackObject(RC.getSize(), RC.getAlignment())); + } + + bool ShouldOptimizeForSize = shouldOptimizeForSize(MF); + + // Do nothing if we are not optimizing for size. + if (!ShouldOptimizeForSize || DisableProEpilogCodeMerge) + return; + + // Adjust the used callee save registers to be a multiple of two as there are + // only library functions for them. + adjustForCalleeSavedRegsSpillCall(MF); +} + +bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, + const TargetRegisterInfo *TRI, std::vector &CSI) const { + const Function &F = *MF.getFunction(); + DEBUG(dbgs() << __func__ << " on " << F.getName() << '\n'); + MachineFrameInfo *MFI = MF.getFrameInfo(); + unsigned NR = TRI->getNumRegs(); + BitVector SRegs(NR); + + // Generate a set of unique, callee-saved registers (SRegs), where each + // register in the set is maximal in terms of sub-/super-register relation, + // i.e. for each R in SRegs, no proper super-register of R is also in SRegs. + + // 1a. For each callee-saved register, add that register to SRegs. + DEBUG(dbgs() << "Initial CS registers: {"); + for (unsigned i = 0, n = CSI.size(); i < n; ++i) { + unsigned R = CSI[i].getReg(); + DEBUG(dbgs() << ' ' << PrintReg(R, TRI)); + for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) + SRegs[*SR] = true; + } + DEBUG(dbgs() << " }\n"); + + // 1b. Collect all registers that have at least one sub-registers in SRegs. + BitVector TmpSup(NR); + for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { + unsigned R = x; + for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) + TmpSup[*SR] = true; + } + // 1c. Out of all the super-registers found in 1b, add to SRegs those of + // them, whose all sub-registers are already in SReg, or will be added to + // SReg (i.e. are in TmpSup). + // At the end of this step, the following will be true: + // R \in SRegs => (if S is sub-register of R, then S \in SRegs) + // S1..Sn = { sub-registers of R }, and S1..Sn \in SRegs => R \in SRegs + for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) { + unsigned R = x; + bool AllSub = true; + for (MCSubRegIterator SR(R, TRI); SR.isValid(); ++SR) { + if (SRegs[*SR] || TmpSup[*SR]) + continue; + AllSub = false; + break; + } + // On Hexagon, a super-register is covered by its sub-registers. + if (AllSub) + SRegs[R] = true; + } + + // 2. For each reserved register, remove that register and all of its + // sub- and super-registers from SRegs. + BitVector Reserved = TRI->getReservedRegs(MF); + for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) { + unsigned R = x; + for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) + SRegs[*SR] = false; + for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) + SRegs[*SR] = false; + } + + // 3. For each register R in SRegs, if any super-register of R is in SRegs, + // remove R from SRegs. + for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { + unsigned R = x; + for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) { + if (!SRegs[*SR]) + continue; + SRegs[R] = false; + break; + } + } + + // Now, for each register that has a fixed stack slot, create the stack + // object for it. + CSI.clear(); + + typedef TargetFrameLowering::SpillSlot SpillSlot; + unsigned NumFixed; + int MinOffset = 0; // CS offsets are negative. + const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed); + for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) { + if (!SRegs[S->Reg]) + continue; + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); + int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), S->Offset); + MinOffset = std::min(MinOffset, S->Offset); + CSI.push_back(CalleeSavedInfo(S->Reg, FI)); + SRegs[S->Reg] = false; + } + + // There can be some registers that don't have fixed slots. For example, + // we need to store R0-R3 in functions with exception handling. For each + // such register, create a non-fixed stack object. + for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { + unsigned R = x; + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R); + int Off = MinOffset - RC->getSize(); + unsigned Align = std::min(RC->getAlignment(), getStackAlignment()); + assert(isPowerOf2_32(Align)); + Off &= -Align; + int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), Off); + MinOffset = std::min(MinOffset, Off); + CSI.push_back(CalleeSavedInfo(R, FI)); + SRegs[R] = false; + } + + DEBUG({ + dbgs() << "CS information: {"; + for (unsigned i = 0, n = CSI.size(); i < n; ++i) { + int FI = CSI[i].getFrameIdx(); + int Off = MFI->getObjectOffset(FI); + dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp"; + if (Off >= 0) + dbgs() << '+'; + dbgs() << Off; + } + dbgs() << " }\n"; + }); + +#ifndef NDEBUG + // Verify that all registers were handled. + bool MissedReg = false; + for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) { + unsigned R = x; + dbgs() << PrintReg(R, TRI) << ' '; + MissedReg = true; + } + if (MissedReg) + llvm_unreachable("...there are unhandled callee-saved registers!"); +#endif + + return true; +} + +void HexagonFrameLowering::expandAlloca(MachineInstr *AI, + const HexagonInstrInfo &TII, unsigned SP, unsigned CF) const { + MachineBasicBlock &MB = *AI->getParent(); + DebugLoc DL = AI->getDebugLoc(); + unsigned A = AI->getOperand(2).getImm(); + + // Have + // Rd = alloca Rs, #A + // + // If Rs and Rd are different registers, use this sequence: + // Rd = sub(r29, Rs) + // r29 = sub(r29, Rs) + // Rd = and(Rd, #-A) ; if necessary + // r29 = and(r29, #-A) ; if necessary + // Rd = add(Rd, #CF) ; CF size aligned to at most A + // otherwise, do + // Rd = sub(r29, Rs) + // Rd = and(Rd, #-A) ; if necessary + // r29 = Rd + // Rd = add(Rd, #CF) ; CF size aligned to at most A + + MachineOperand &RdOp = AI->getOperand(0); + MachineOperand &RsOp = AI->getOperand(1); + unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); + + // Rd = sub(r29, Rs) + BuildMI(MB, AI, DL, TII.get(Hexagon::A2_sub), Rd) + .addReg(SP) + .addReg(Rs); + if (Rs != Rd) { + // r29 = sub(r29, Rs) + BuildMI(MB, AI, DL, TII.get(Hexagon::A2_sub), SP) + .addReg(SP) + .addReg(Rs); + } + if (A > 8) { + // Rd = and(Rd, #-A) + BuildMI(MB, AI, DL, TII.get(Hexagon::A2_andir), Rd) + .addReg(Rd) + .addImm(-int64_t(A)); + if (Rs != Rd) + BuildMI(MB, AI, DL, TII.get(Hexagon::A2_andir), SP) + .addReg(SP) + .addImm(-int64_t(A)); + } + if (Rs == Rd) { + // r29 = Rd + BuildMI(MB, AI, DL, TII.get(TargetOpcode::COPY), SP) + .addReg(Rd); + } + if (CF > 0) { + // Rd = add(Rd, #CF) + BuildMI(MB, AI, DL, TII.get(Hexagon::A2_addi), Rd) + .addReg(Rd) + .addImm(CF); + } +} + +bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + if (!MFI->hasVarSizedObjects()) + return false; + unsigned MaxA = MFI->getMaxAlignment(); + if (MaxA <= getStackAlignment()) + return false; + return true; +} + +MachineInstr *HexagonFrameLowering::getAlignaInstr(MachineFunction &MF) const { + for (auto &B : MF) + for (auto &I : B) + if (I.getOpcode() == Hexagon::ALIGNA) + return &I; + return nullptr; +} + diff --git a/lib/Target/Hexagon/HexagonFrameLowering.h b/lib/Target/Hexagon/HexagonFrameLowering.h index 2d6b4579380..dfecef96cf1 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/lib/Target/Hexagon/HexagonFrameLowering.h @@ -15,17 +15,22 @@ namespace llvm { +class HexagonInstrInfo; + class HexagonFrameLowering : public TargetFrameLowering { private: - void determineFrameLayout(MachineFunction &MF) const; + void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII, + unsigned SP, unsigned CF) const; public: - explicit HexagonFrameLowering() : TargetFrameLowering(StackGrowsDown, 8, 0) {} + explicit HexagonFrameLowering() + : TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {} - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. void emitPrologue(MachineFunction &MF) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + bool targetHandlesStackFrameRounding() const override { + return true; + } bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, @@ -41,9 +46,37 @@ public: MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const override; + void processFunctionBeforeFrameFinalized(MachineFunction &MF, + RegScavenger *RS = NULL) const override; + void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS) const override; int getFrameIndexOffset(const MachineFunction &MF, int FI) const override; bool hasFP(const MachineFunction &MF) const override; bool hasTailCall(MachineBasicBlock &MBB) const; + void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const; + bool replacePredRegPseudoSpillCode(MachineFunction &MF) const; + + const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) + const override { + static const SpillSlot Offsets[] = { + { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, + { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, + { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, + { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 }, + { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, + { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } + }; + + NumEntries = array_lengthof(Offsets); + return Offsets; + } + + bool assignCalleeSavedSpillSlots(MachineFunction &MF, + const TargetRegisterInfo *TRI, + std::vector &CSI) const override; + + bool needsAligna(const MachineFunction &MF) const; + MachineInstr *getAlignaInstr(MachineFunction &MF) const; }; } // End llvm namespace diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index aaccac8b57a..d02c6eeb3b9 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -13,8 +13,11 @@ #include "Hexagon.h" #include "HexagonISelLowering.h" +#include "HexagonMachineFunctionInfo.h" #include "HexagonTargetMachine.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/CodeGen/FunctionLoweringInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/IR/Intrinsics.h" #include "llvm/Support/CommandLine.h" @@ -62,6 +65,7 @@ public: } virtual void PreprocessISelDAG() override; + virtual void EmitFunctionEntryCode() override; SDNode *Select(SDNode *N) override; @@ -1216,12 +1220,30 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) { SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) { + MachineFrameInfo *MFI = MF->getFrameInfo(); + const HexagonFrameLowering *HFI = HST->getFrameLowering(); int FX = cast(N)->getIndex(); + unsigned StkA = HFI->getStackAlignment(); + unsigned MaxA = MFI->getMaxAlignment(); SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32); SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32); SDLoc DL(N); + SDNode *R = 0; - SDNode *R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero); + // Use TFR_FI when: + // - the object is fixed, or + // - there are no objects with higher-than-default alignment, or + // - there are no dynamically allocated objects. + // Otherwise, use TFR_FIA. + if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) { + R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero); + } else { + auto &HMFI = *MF->getInfo(); + unsigned AR = HMFI.getStackAlignBaseVReg(); + SDValue CH = CurDAG->getEntryNode(); + SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero }; + R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops); + } if (N->getHasDebugValue()) CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0)); @@ -1280,7 +1302,6 @@ SDNode *HexagonDAGToDAGISel::Select(SDNode *N) { return SelectCode(N); } - bool HexagonDAGToDAGISel:: SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { @@ -1352,12 +1373,32 @@ void HexagonDAGToDAGISel::PreprocessISelDAG() { } } +void HexagonDAGToDAGISel::EmitFunctionEntryCode() { + auto &HST = static_cast(MF->getSubtarget()); + auto &HFI = *HST.getFrameLowering(); + if (!HFI.needsAligna(*MF)) + return; + MachineFrameInfo *MFI = MF->getFrameInfo(); + MachineBasicBlock *EntryBB = MF->begin(); + unsigned AR = FuncInfo->CreateReg(MVT::i32); + unsigned MaxA = MFI->getMaxAlignment(); + auto &HII = *HST.getInstrInfo(); + BuildMI(EntryBB, DebugLoc(), HII.get(Hexagon::ALIGNA), AR) + .addImm(MaxA); + MF->getInfo()->setStackAlignBaseVReg(AR); +} + +// Match a frame index that can be used in an addressing mode. bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) { if (N.getOpcode() != ISD::FrameIndex) return false; - FrameIndexSDNode *FX = cast(N); - R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32); + auto &HFI = *HST->getFrameLowering(); + MachineFrameInfo *MFI = MF->getFrameInfo(); + int FX = cast(N)->getIndex(); + if (!MFI->isFixedObjectIndex(FX) && HFI.needsAligna(*MF)) + return false; + R = CurDAG->getTargetFrameIndex(FX, MVT::i32); return true; } diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 63900e02042..0a17abc6f64 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -420,6 +420,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, bool doesNotReturn = CLI.DoesNotReturn; bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); + MachineFunction &MF = DAG.getMachineFunction(); // Check for varargs. int NumNamedVarArgParams = -1; @@ -444,41 +445,40 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), NumNamedVarArgParams); - if (NumNamedVarArgParams > 0) + if (isVarArg) CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); else CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); + if (DAG.getTarget().Options.DisableTailCalls) + isTailCall = false; - if(isTailCall) { - bool StructAttrFlag = - DAG.getMachineFunction().getFunction()->hasStructRetAttr(); + if (isTailCall) { + bool StructAttrFlag = MF.getFunction()->hasStructRetAttr(); isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, IsStructRet, StructAttrFlag, Outs, OutVals, Ins, DAG); - for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){ + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; if (VA.isMemLoc()) { isTailCall = false; break; } } - if (isTailCall) { - DEBUG(dbgs () << "Eligible for Tail Call\n"); - } else { - DEBUG(dbgs () << - "Argument must be passed on stack. Not eligible for Tail Call\n"); - } + DEBUG(dbgs() << (isTailCall ? "Eligible for Tail Call\n" + : "Argument must be passed on stack. " + "Not eligible for Tail Call\n")); } // Get a count of how many bytes are to be pushed on the stack. unsigned NumBytes = CCInfo.getNextStackOffset(); SmallVector, 16> RegsToPass; SmallVector MemOpChains; - const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); - SDValue StackPtr = - DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy()); + auto &HRI = + static_cast(*Subtarget->getRegisterInfo()); + SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), + getPointerTy()); // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { @@ -491,6 +491,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, default: // Loc info must be one of Full, SExt, ZExt, or AExt. llvm_unreachable("Unknown loc info!"); + case CCValAssign::BCvt: case CCValAssign::Full: break; case CCValAssign::SExt: @@ -506,41 +507,37 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (VA.isMemLoc()) { unsigned LocMemOffset = VA.getLocMemOffset(); - SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType()); - PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); - + SDValue MemAddr = DAG.getConstant(LocMemOffset, StackPtr.getValueType()); + MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); if (Flags.isByVal()) { // The argument is a struct passed by value. According to LLVM, "Arg" // is is pointer. - MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain, + MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain, Flags, DAG, dl)); } else { - // The argument is not passed by value. "Arg" is a buildin type. It is - // not a pointer. - MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, - MachinePointerInfo(),false, false, - 0)); + MachinePointerInfo LocPI = MachinePointerInfo::getStack(LocMemOffset); + SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI, false, + false, 0); + MemOpChains.push_back(S); } continue; } // Arguments that can be passed on register must be kept at RegsToPass // vector. - if (VA.isRegLoc()) { + if (VA.isRegLoc()) RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - } } // Transform all store nodes into one single node because all store // nodes are independent of each other. - if (!MemOpChains.empty()) { + if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); - } - if (!isTailCall) - Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, - getPointerTy(), true), - dl); + if (!isTailCall) { + SDValue C = DAG.getConstant(NumBytes, getPointerTy(), true); + Chain = DAG.getCALLSEQ_START(Chain, C, dl); + } // Build a sequence of copy-to-reg nodes chained together with token // chain and flag operands which copy the outgoing args into registers. @@ -553,10 +550,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } - } - - // For tail calls lower the arguments to the 'real' stack slot. - if (isTailCall) { + } else { + // For tail calls lower the arguments to the 'real' stack slot. + // // Force all the incoming stack arguments to be loaded from the stack // before any new outgoing arguments are stored to the stack, because the // outgoing stack slots may alias the incoming argument stack slots, and @@ -571,7 +567,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second, InFlag); InFlag = Chain.getValue(1); } - InFlag =SDValue(); + InFlag = SDValue(); } // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every @@ -580,8 +576,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (flag_aligned_memcpy) { const char *MemcpyName = "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes"; - Callee = - DAG.getTargetExternalSymbol(MemcpyName, getPointerTy()); + Callee = DAG.getTargetExternalSymbol(MemcpyName, getPointerTy()); flag_aligned_memcpy = false; } else if (GlobalAddressSDNode *G = dyn_cast(Callee)) { Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); @@ -603,9 +598,8 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second.getValueType())); } - if (InFlag.getNode()) { + if (InFlag.getNode()) Ops.push_back(InFlag); - } if (isTailCall) return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops); @@ -630,7 +624,7 @@ static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, SDValue &Offset, bool &isInc, SelectionDAG &DAG) { if (Ptr->getOpcode() != ISD::ADD) - return false; + return false; if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { isInc = (Ptr->getOpcode() == ISD::ADD); @@ -702,8 +696,7 @@ SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const { SDNode *Node = Op.getNode(); MachineFunction &MF = DAG.getMachineFunction(); - HexagonMachineFunctionInfo *FuncInfo = - MF.getInfo(); + auto &FuncInfo = *MF.getInfo(); switch (Node->getOpcode()) { case ISD::INLINEASM: { unsigned NumOps = Node->getNumOperands(); @@ -711,7 +704,7 @@ SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, --NumOps; // Ignore the flag operand. for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { - if (FuncInfo->hasClobberLR()) + if (FuncInfo.hasClobberLR()) break; unsigned Flags = cast(Node->getOperand(i))->getZExtValue(); @@ -736,7 +729,7 @@ SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, // Check it to be lr const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); if (Reg == QRI->getRARegister()) { - FuncInfo->setHasClobberLR(true); + FuncInfo.setHasClobberLR(true); break; } } @@ -795,43 +788,28 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); + SDValue Align = Op.getOperand(2); SDLoc dl(Op); - unsigned SPReg = getStackPointerRegisterToSaveRestore(); + ConstantSDNode *AlignConst = dyn_cast(Align); + assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC"); - // Get a reference to the stack pointer. - SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); + unsigned A = AlignConst->getSExtValue(); + auto &HST = static_cast(DAG.getSubtarget()); + auto &HFI = *HST.getFrameLowering(); + // "Zero" means natural stack alignment. + if (A == 0) + A = HFI.getStackAlignment(); - // Subtract the dynamic size from the actual stack size to - // obtain the new stack size. - SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); + DEBUG({ + dbgs () << __func__ << " Align: " << A << " Size: "; + Size.getNode()->dump(&DAG); + dbgs() << "\n"; + }); - // - // For Hexagon, the outgoing memory arguments area should be on top of the - // alloca area on the stack i.e., the outgoing memory arguments should be - // at a lower address than the alloca area. Move the alloca area down the - // stack by adding back the space reserved for outgoing arguments to SP - // here. - // - // We do not know what the size of the outgoing args is at this point. - // So, we add a pseudo instruction ADJDYNALLOC that will adjust the - // stack pointer. We patch this instruction with the correct, known - // offset in emitPrologue(). - // - // Use a placeholder immediate (zero) for now. This will be patched up - // by emitPrologue(). - SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl, - MVT::i32, - Sub, - DAG.getConstant(0, MVT::i32)); - - // The Sub result contains the new stack start address, so it - // must be placed in the stack pointer register. - const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo(); - SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub); - - SDValue Ops[2] = { ArgAdjust, CopyChain }; - return DAG.getMergeValues(Ops, dl); + SDValue AC = DAG.getConstant(A, MVT::i32); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + return DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC); } SDValue @@ -847,9 +825,7 @@ const { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - HexagonMachineFunctionInfo *FuncInfo = - MF.getInfo(); - + auto &FuncInfo = *MF.getInfo(); // Assign locations to all of the incoming arguments. SmallVector ArgLocs; @@ -938,7 +914,7 @@ const { HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset(), true); - FuncInfo->setVarArgsFrameIndex(FrameIndex); + FuncInfo.setVarArgsFrameIndex(FrameIndex); } return Chain; @@ -1795,7 +1771,7 @@ HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::CONST32: return "HexagonISD::CONST32"; case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP"; case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real"; - case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC"; + case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA"; case HexagonISD::CMPICC: return "HexagonISD::CMPICC"; case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC"; case HexagonISD::BRICC: return "HexagonISD::BRICC"; @@ -2419,20 +2395,14 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { } } - - -//===----------------------------------------------------------------------===// -// Hexagon Scheduler Hooks -//===----------------------------------------------------------------------===// MachineBasicBlock * HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) -const { + const { switch (MI->getOpcode()) { - case Hexagon::ADJDYNALLOC: { + case Hexagon::ALLOCA: { MachineFunction *MF = BB->getParent(); - HexagonMachineFunctionInfo *FuncInfo = - MF->getInfo(); + auto *FuncInfo = MF->getInfo(); FuncInfo->addAllocaAdjustInst(MI); return BB; } diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 34b1ebb4d3e..e4a9961a1be 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -34,7 +34,7 @@ bool isPositiveHalfWord(SDNode *N); CONST32_Int_Real, FCONST32, SETCC, - ADJDYNALLOC, + ALLOCA, ARGEXTEND, PIC_ADD, diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index ff4bcadaabb..08330a35855 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -573,6 +573,12 @@ HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { unsigned Opc = MI->getOpcode(); switch (Opc) { + case Hexagon::ALIGNA: + BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg()) + .addReg(TRI.getFrameRegister()) + .addImm(-MI->getOperand(1).getImm()); + MBB.erase(MI); + return true; case Hexagon::TFR_PdTrue: { unsigned Reg = MI->getOperand(0).getReg(); BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 19cf9932452..d297c7535be 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -4526,10 +4526,18 @@ def Y2_barrier : SYSInst<(outs), (ins), // SYSTEM/SUPER - //===----------------------------------------------------------------------===// -// Generate frameindex addresses. +// Generate frameindex addresses. The main reason for the offset operand is +// that every instruction that is allowed to have frame index as an operand +// will then have that operand followed by an immediate operand (the offset). +// This simplifies the frame-index elimination code. +// let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, - isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in -def TFR_FI: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$fi, s32Imm:$Off), "">; + isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { + def TFR_FI : ALU32_ri<(outs IntRegs:$Rd), + (ins IntRegs:$fi, s32Imm:$off), "">; + def TFR_FIA : ALU32_ri<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">; +} //===----------------------------------------------------------------------===// // CRUSER - Type. @@ -5105,21 +5113,25 @@ def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)), )>; // Hexagon specific ISD nodes. -def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, - SDTCisVT<1, i32>]>; -def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>; +def SDTHexagonALLOCA : SDTypeProfile<1, 2, + [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA, + [SDNPHasChain]>; -def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC", - SDTHexagonADJDYNALLOC>; -def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>; +// The reason for the custom inserter is to record all ALLOCA instructions +// in MachineFunctionInfo. +let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1, + usesCustomInserter = 1 in +def ALLOCA: ALU32Inst<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, u32Imm:$A), "", + [(set (i32 IntRegs:$Rd), + (HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>; -// Needed to tag these instructions for stack layout. -let isCodeGenOnly = 1, usesCustomInserter = 1 in -def ADJDYNALLOC : T_Addri; - -def: Pat<(Hexagon_ADJDYNALLOC I32:$Rs, s16ImmPred:$s16), - (ADJDYNALLOC I32:$Rs, imm:$s16)>; +let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in +def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>; +def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>; +def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>; let isCodeGenOnly = 1 in def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1), "$dst = $src1", diff --git a/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/lib/Target/Hexagon/HexagonMachineFunctionInfo.h index cb18df6ed19..76723586c66 100644 --- a/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ b/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -27,6 +27,7 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo { // returning the value of the returned struct in a register. This field // holds the virtual register into which the sret argument is passed. unsigned SRetReturnReg; + unsigned StackAlignBaseReg; std::vector AllocaAdjustInsts; int VarArgsFrameIndex; bool HasClobberLR; @@ -35,10 +36,11 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo { virtual void anchor(); public: - HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0), - HasEHReturn(false) {} + HexagonMachineFunctionInfo() : SRetReturnReg(0), StackAlignBaseReg(0), + HasClobberLR(0), HasEHReturn(false) {} HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0), + StackAlignBaseReg(0), HasClobberLR(0), HasEHReturn(false) {} @@ -74,6 +76,9 @@ public: bool hasEHReturn() const { return HasEHReturn; }; void setHasEHReturn(bool H = true) { HasEHReturn = H; }; + + void setStackAlignBaseVReg(unsigned R) { StackAlignBaseReg = R; } + unsigned getStackAlignBaseVReg() const { return StackAlignBaseReg; } }; } // End llvm namespace diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 86eaee8ddbc..8f255a08f53 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -30,7 +30,9 @@ #include "llvm/IR/Type.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -40,6 +42,37 @@ using namespace llvm; HexagonRegisterInfo::HexagonRegisterInfo() : HexagonGenRegisterInfo(Hexagon::R31) {} + +bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { + return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || + R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; +} + +bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const { + return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; +} + + +const MCPhysReg * +HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF) const { + static const MCPhysReg CallerSavedRegsV4[] = { + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, + Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, + Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, + Hexagon::R15, 0 + }; + + auto &HST = static_cast(MF->getSubtarget()); + switch (HST.getHexagonArchVersion()) { + case HexagonSubtarget::V4: + case HexagonSubtarget::V5: + return CallerSavedRegsV4; + } + llvm_unreachable( + "Callee saved registers requested for unknown archtecture version"); +} + + const MCPhysReg * HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { static const MCPhysReg CalleeSavedRegsV3[] = { @@ -75,173 +108,153 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) } -const TargetRegisterClass* const* -HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { - static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = { - &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass, - &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass, - &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass, - &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass, - &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass, - &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass, - }; - - switch (MF->getSubtarget().getHexagonArchVersion()) { - case HexagonSubtarget::V4: - case HexagonSubtarget::V5: - return CalleeSavedRegClassesV3; - } - llvm_unreachable("Callee saved register classes requested for unknown " - "architecture version"); -} - void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, unsigned FIOperandNum, + int SPAdj, unsigned FIOp, RegScavenger *RS) const { // // Hexagon_TODO: Do we need to enforce this for Hexagon? assert(SPAdj == 0 && "Unexpected"); MachineInstr &MI = *II; - int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - // Addressable stack objects are accessed using neg. offsets from %fp. - MachineFunction &MF = *MI.getParent()->getParent(); - const HexagonInstrInfo &TII = - *static_cast(MF.getSubtarget().getInstrInfo()); - int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); + MachineBasicBlock &MB = *MI.getParent(); + MachineFunction &MF = *MB.getParent(); MachineFrameInfo &MFI = *MF.getFrameInfo(); + auto &HST = static_cast(MF.getSubtarget()); + auto &HII = *HST.getInstrInfo(); + auto &HFI = *HST.getFrameLowering(); - unsigned FrameReg = getFrameRegister(MF); - const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - if (!TFI->hasFP(MF)) { + int FI = MI.getOperand(FIOp).getIndex(); + int Offset = MFI.getObjectOffset(FI) + MI.getOperand(FIOp+1).getImm(); + bool HasAlloca = MFI.hasVarSizedObjects(); + bool HasAlign = needsStackRealignment(MF); + + // XXX: Fixed objects cannot be accessed through SP if there are aligned + // objects in the local frame, or if there are dynamically allocated objects. + // In such cases, there has to be FP available. + if (!HFI.hasFP(MF)) { + assert(!HasAlloca && !HasAlign && "This function must have frame pointer"); // We will not reserve space on the stack for the lr and fp registers. - Offset -= 2 * Hexagon_WordSize; + Offset -= 8; } + unsigned SP = getStackRegister(), FP = getFrameRegister(); + unsigned AP = 0; + if (MachineInstr *AI = HFI.getAlignaInstr(MF)) + AP = AI->getOperand(0).getReg(); unsigned FrameSize = MFI.getStackSize(); - if (MI.getOpcode() == Hexagon::TFR_FI) - MI.setDesc(TII.get(Hexagon::A2_addi)); - if (!MFI.hasVarSizedObjects() && - TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && - !TII.isSpillPredRegOp(&MI)) { - // Replace frame index with a stack pointer reference. - MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false, - false, true); - MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset); + // Special handling of dbg_value instructions and INLINEASM. + if (MI.isDebugValue() || MI.isInlineAsm()) { + MI.getOperand(FIOp).ChangeToRegister(SP, false /*isDef*/); + MI.getOperand(FIOp+1).ChangeToImmediate(Offset+FrameSize); + return; + } + + bool UseFP = false, UseAP = false; // Default: use SP. + if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) { + UseFP = HasAlloca || HasAlign; } else { - // Replace frame index with a frame pointer reference. - if (!TII.isValidOffset(MI.getOpcode(), Offset)) { - - // If the offset overflows, then correct it. - // - // For loads, we do not need a reserved register - // r0 = memw(r30 + #10000) to: - // - // r0 = add(r30, #10000) - // r0 = memw(r0) - if ( (MI.getOpcode() == Hexagon::L2_loadri_io) || - (MI.getOpcode() == Hexagon::L2_loadrd_io) || - (MI.getOpcode() == Hexagon::L2_loadrh_io) || - (MI.getOpcode() == Hexagon::L2_loadruh_io) || - (MI.getOpcode() == Hexagon::L2_loadrb_io) || - (MI.getOpcode() == Hexagon::L2_loadrub_io)) { - unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ? - getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) : - MI.getOperand(0).getReg(); - - // Check if offset can fit in addi. - if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) { - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::A2_add), - dstReg).addReg(FrameReg).addReg(dstReg); - } else { - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::A2_addi), - dstReg).addReg(FrameReg).addImm(Offset); - } - - MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true); - MI.getOperand(FIOperandNum+1).ChangeToImmediate(0); - } else if ((MI.getOpcode() == Hexagon::S2_storeri_io) || - (MI.getOpcode() == Hexagon::S2_storerd_io) || - (MI.getOpcode() == Hexagon::S2_storerh_io) || - (MI.getOpcode() == Hexagon::S2_storerb_io)) { - // For stores, we need a reserved register. Change - // memw(r30 + #10000) = r0 to: - // - // rs = add(r30, #10000); - // memw(rs) = r0 - unsigned resReg = HEXAGON_RESERVED_REG_1; - - // Check if offset can fit in addi. - if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) { - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset); - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::A2_add), - resReg).addReg(FrameReg).addReg(resReg); - } else { - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::A2_addi), - resReg).addReg(FrameReg).addImm(Offset); - } - MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true); - MI.getOperand(FIOperandNum+1).ChangeToImmediate(0); - } else if (TII.isMemOp(&MI)) { - // use the constant extender if the instruction provides it - if (TII.isConstExtended(&MI)) { - MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false); - MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset); - TII.immediateExtend(&MI); - } else { - llvm_unreachable("Need to implement for memops"); - } - } else { - unsigned dstReg = MI.getOperand(0).getReg(); - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset); - BuildMI(*MI.getParent(), II, MI.getDebugLoc(), - TII.get(Hexagon::A2_add), - dstReg).addReg(FrameReg).addReg(dstReg); - // Can we delete MI??? r2 = add (r2, #0). - MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true); - MI.getOperand(FIOperandNum+1).ChangeToImmediate(0); - } - } else { - // If the offset is small enough to fit in the immediate field, directly - // encode it. - MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false); - MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset); + if (HasAlloca) { + if (HasAlign) + UseAP = true; + else + UseFP = true; } } + unsigned Opc = MI.getOpcode(); + bool ValidSP = HII.isValidOffset(Opc, FrameSize+Offset); + bool ValidFP = HII.isValidOffset(Opc, Offset); + + // Calculate the actual offset in the instruction. + int64_t RealOffset = Offset; + if (!UseFP && !UseAP) + RealOffset = FrameSize+Offset; + + switch (Opc) { + case Hexagon::TFR_FIA: + MI.setDesc(HII.get(Hexagon::A2_addi)); + MI.getOperand(FIOp).ChangeToImmediate(RealOffset); + MI.RemoveOperand(FIOp+1); + return; + case Hexagon::TFR_FI: + // Set up the instruction for updating below. + MI.setDesc(HII.get(Hexagon::A2_addi)); + break; + } + + unsigned BP = 0; + bool Valid = false; + if (UseFP) { + BP = FP; + Valid = ValidFP; + } else if (UseAP) { + BP = AP; + Valid = ValidFP; + } else { + BP = SP; + Valid = ValidSP; + } + + if (Valid) { + MI.getOperand(FIOp).ChangeToRegister(BP, false); + MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset); + return; + } + +#ifndef NDEBUG + const Function *F = MF.getFunction(); + dbgs() << "In function "; + if (F) dbgs() << F->getName(); + else dbgs() << ""; + dbgs() << ", BB#" << MB.getNumber() << "\n" << MI; +#endif + llvm_unreachable("Unhandled instruction"); } + unsigned HexagonRegisterInfo::getRARegister() const { return Hexagon::R31; } + unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - if (TFI->hasFP(MF)) { + if (TFI->hasFP(MF)) return Hexagon::R30; - } - return Hexagon::R29; } + unsigned HexagonRegisterInfo::getFrameRegister() const { return Hexagon::R30; } + unsigned HexagonRegisterInfo::getStackRegister() const { return Hexagon::R29; } + +bool +HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { + return MF.getSubtarget().getFrameLowering()->hasFP(MF); +} + + +bool +HexagonRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + return MFI->getMaxAlignment() > 8; +} + + +unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const { + return Hexagon::R6; +} + + #define GET_REGINFO_TARGET_DESC #include "HexagonGenRegisterInfo.inc" diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h index dc6dd2a156f..ff7b1731209 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -43,25 +43,29 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo { /// Code Generation virtual methods... const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; - const TargetRegisterClass* const* - getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const; BitVector getReservedRegs(const MachineFunction &MF) const override; - void eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, unsigned FIOperandNum, - RegScavenger *RS = nullptr) const override; + void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, + unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; - /// determineFrameLayout - Determine the size of the frame and maximum call - /// frame size. - void determineFrameLayout(MachineFunction &MF) const; - - /// requiresRegisterScavenging - returns true since we may need scavenging for - /// a temporary register when generating hardware loop instructions. + /// Returns true since we may need scavenging for a temporary register + /// when generating hardware loop instructions. bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; } + /// Returns true. Spill code for predicate registers might need an extra + /// register. + bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { + return true; + } + + bool needsStackRealignment(const MachineFunction &MF) const override; + + /// Returns true if the frame pointer is valid. + bool useFPForScavengingIndex(const MachineFunction &MF) const override; + bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { return true; } @@ -71,6 +75,12 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo { unsigned getFrameRegister(const MachineFunction &MF) const override; unsigned getFrameRegister() const; unsigned getStackRegister() const; + + const uint16_t *getCallerSavedRegs(const MachineFunction *MF) const; + unsigned getFirstCallerSavedNonParamReg() const; + + bool isEHReturnCalleeSaveReg(unsigned Reg) const; + bool isCalleeSaveReg(unsigned Reg) const; }; } // end namespace llvm