mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
- movlp{s|d} and movhp{s|d} support.
- Normalize shuffle nodes so result vector lower half elements come from the first vector, the rest come from the second vector. (Except for the exceptions :-). - Other minor fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -1404,6 +1404,16 @@ static bool DarwinGVRequiresExtraLoad(GlobalValue *GV) {
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(GV->isExternal() && !GV->hasNotBeenReadFromBytecode()));
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}
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/// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
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/// true if Op is undef or if its value falls within the specified range (L, H).
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static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
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if (Op.getOpcode() == ISD::UNDEF)
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return true;
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unsigned Val = cast<ConstantSDNode>(Op)->getValue();
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return (Val >= Low && Val <= Hi);
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}
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/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to PSHUFD.
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bool X86::isPSHUFDMask(SDNode *N) {
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@ -1491,24 +1501,17 @@ bool X86::isSHUFPMask(SDNode *N) {
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unsigned NumElems = N->getNumOperands();
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if (NumElems == 2) {
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// The only case that ought be handled by SHUFPD is
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// The only cases that ought be handled by SHUFPD is
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// Dest { 2, 1 } <= shuffle( Dest { 1, 0 }, Src { 3, 2 }
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// Dest { 3, 0 } <= shuffle( Dest { 1, 0 }, Src { 3, 2 }
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// Expect bit 0 == 1, bit1 == 2
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SDOperand Bit0 = N->getOperand(0);
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if (Bit0.getOpcode() != ISD::UNDEF) {
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assert(isa<ConstantSDNode>(Bit0) && "Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(Bit0)->getValue() != 1)
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return false;
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}
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SDOperand Bit1 = N->getOperand(1);
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if (Bit1.getOpcode() != ISD::UNDEF) {
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assert(isa<ConstantSDNode>(Bit1) && "Invalid VECTOR_SHUFFLE mask!");
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if (cast<ConstantSDNode>(Bit1)->getValue() != 2)
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return false;
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}
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if (isUndefOrInRange(Bit0, 0, 0) && isUndefOrInRange(Bit1, 3, 3))
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return true;
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if (isUndefOrInRange(Bit0, 1, 1) && isUndefOrInRange(Bit1, 2, 2))
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return true;
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return false;
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}
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if (NumElems != 4) return false;
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@ -1614,6 +1617,62 @@ bool X86::isMOVLHPSMask(SDNode *N) {
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return true;
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}
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/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
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bool X86::isMOVLPMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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unsigned NumElems = N->getNumOperands();
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if (NumElems != 2 && NumElems != 4)
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return false;
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for (unsigned i = 0; i < NumElems/2; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != i + NumElems) return false;
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}
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for (unsigned i = NumElems/2; i < NumElems; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != i) return false;
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}
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return true;
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}
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/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}.
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bool X86::isMOVHPMask(SDNode *N) {
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assert(N->getOpcode() == ISD::BUILD_VECTOR);
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unsigned NumElems = N->getNumOperands();
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if (NumElems != 2 && NumElems != 4)
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return false;
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for (unsigned i = 0; i < NumElems/2; ++i) {
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SDOperand Arg = N->getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != i) return false;
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}
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for (unsigned i = 0; i < NumElems/2; ++i) {
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SDOperand Arg = N->getOperand(i + NumElems/2);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val != i + NumElems) return false;
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}
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return true;
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}
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool X86::isUNPCKLMask(SDNode *N) {
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@ -1786,42 +1845,6 @@ unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
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return Mask;
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}
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/// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as
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/// values in ther permute mask if needed. Use V1 as second vector if it is
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/// undef. Return an empty SDOperand is it is already well formed.
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static SDOperand NormalizeVectorShuffle(SDOperand Op, SelectionDAG &DAG) {
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SDOperand V1 = Op.getOperand(0);
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SDOperand V2 = Op.getOperand(1);
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SDOperand Mask = Op.getOperand(2);
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MVT::ValueType VT = Op.getValueType();
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unsigned NumElems = Mask.getNumOperands();
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SDOperand Half1 = Mask.getOperand(0);
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SDOperand Half2 = Mask.getOperand(NumElems/2);
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bool V2Undef = false;
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if (V2.getOpcode() == ISD::UNDEF) {
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V2Undef = true;
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V2 = V1;
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}
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if (cast<ConstantSDNode>(Half1)->getValue() >= NumElems &&
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cast<ConstantSDNode>(Half2)->getValue() < NumElems) {
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// Swap the operands and change mask.
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std::vector<SDOperand> MaskVec;
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for (unsigned i = NumElems / 2; i != NumElems; ++i)
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MaskVec.push_back(Mask.getOperand(i));
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for (unsigned i = 0; i != NumElems / 2; ++i)
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MaskVec.push_back(Mask.getOperand(i));
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Mask =
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DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
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}
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if (V2Undef)
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
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return Op;
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}
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/// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
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/// specifies a 8 element shuffle that can be broken into a pair of
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/// PSHUFHW and PSHUFLW.
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@ -1854,6 +1877,81 @@ static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
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return true;
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}
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/// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
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/// values in ther permute mask.
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static SDOperand CommuteVectorShuffle(SDOperand Op, SelectionDAG &DAG) {
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SDOperand V1 = Op.getOperand(0);
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SDOperand V2 = Op.getOperand(1);
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SDOperand Mask = Op.getOperand(2);
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType MaskVT = Mask.getValueType();
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MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
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unsigned NumElems = Mask.getNumOperands();
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std::vector<SDOperand> MaskVec;
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for (unsigned i = 0; i != NumElems; ++i) {
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SDOperand Arg = Mask.getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
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unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
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if (Val < NumElems)
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MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
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else
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MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
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}
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Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
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}
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/// isScalarLoadToVector - Returns true if the node is a scalar load that
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/// is promoted to a vector.
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static inline bool isScalarLoadToVector(SDOperand Op) {
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if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR) {
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Op = Op.getOperand(0);
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return (Op.getOpcode() == ISD::LOAD);
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}
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return false;
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}
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/// ShouldXformedToMOVLP - Return true if the node should be transformed to
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/// match movlp{d|s}. The lower half elements should come from V1 (and in
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/// order), and the upper half elements should come from the upper half of
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/// V2 (not necessarily in order). And since V1 will become the source of
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/// the MOVLP, it must be a scalar load.
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static bool ShouldXformedToMOVLP(SDOperand V1, SDOperand V2, SDOperand Mask) {
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if (isScalarLoadToVector(V1)) {
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unsigned NumElems = Mask.getNumOperands();
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for (unsigned i = 0, e = NumElems/2; i != e; ++i)
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if (!isUndefOrInRange(Mask.getOperand(i), i, i))
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return false;
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for (unsigned i = NumElems/2; i != NumElems; ++i)
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if (!isUndefOrInRange(Mask.getOperand(i),
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NumElems+NumElems/2, NumElems*2-1))
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return false;
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return true;
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}
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return false;
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}
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/// isLowerFromV2UpperFromV1 - Returns true if the shuffle mask is except
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/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
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/// half elements to come from vector 1 (which would equal the dest.) and
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/// the upper half to come from vector 2.
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static bool isLowerFromV2UpperFromV1(SDOperand Op) {
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assert(Op.getOpcode() == ISD::BUILD_VECTOR);
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unsigned NumElems = Op.getNumOperands();
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for (unsigned i = 0, e = NumElems/2; i != e; ++i)
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if (!isUndefOrInRange(Op.getOperand(i), NumElems, NumElems*2-1))
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return false;
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for (unsigned i = NumElems/2; i != NumElems; ++i)
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if (!isUndefOrInRange(Op.getOperand(i), 0, NumElems-1))
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return false;
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return true;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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@ -2638,13 +2736,28 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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unsigned NumElems = PermMask.getNumOperands();
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// Splat && PSHUFD's 2nd vector must be undef.
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if (X86::isSplatMask(PermMask.Val)) {
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if (V2.getOpcode() != ISD::UNDEF)
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
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if (X86::isSplatMask(PermMask.Val))
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return Op;
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// Normalize the node to match x86 shuffle ops if needed
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if (V2.getOpcode() != ISD::UNDEF) {
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bool DoSwap = false;
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if (ShouldXformedToMOVLP(V1, V2, PermMask))
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DoSwap = true;
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else if (isLowerFromV2UpperFromV1(PermMask))
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DoSwap = true;
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if (DoSwap) {
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Op = CommuteVectorShuffle(Op, DAG);
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V1 = Op.getOperand(0);
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V2 = Op.getOperand(1);
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PermMask = Op.getOperand(2);
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}
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}
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if (NumElems == 2)
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return Op;
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if (X86::isUNPCKLMask(PermMask.Val) ||
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X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
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@ -2652,9 +2765,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
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return Op;
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if (NumElems == 2)
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return NormalizeVectorShuffle(Op, DAG);
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// If VT is integer, try PSHUF* first, then SHUFP*.
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if (MVT::isInteger(VT)) {
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if (X86::isPSHUFDMask(PermMask.Val) ||
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@ -2667,7 +2777,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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if (X86::isSHUFPMask(PermMask.Val))
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return NormalizeVectorShuffle(Op, DAG);
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return Op;
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// Handle v8i16 shuffle high / low shuffle node pair.
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if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
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@ -2691,7 +2801,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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} else {
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// Floating point cases in the other order.
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if (X86::isSHUFPMask(PermMask.Val))
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return NormalizeVectorShuffle(Op, DAG);
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return Op;
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if (X86::isPSHUFDMask(PermMask.Val) ||
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X86::isPSHUFHWMask(PermMask.Val) ||
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X86::isPSHUFLWMask(PermMask.Val)) {
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@ -2870,8 +2980,8 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case Intrinsic::x86_sse2_ucomigt_sd:
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case Intrinsic::x86_sse2_ucomige_sd:
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case Intrinsic::x86_sse2_ucomineq_sd: {
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unsigned Opc;
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ISD::CondCode CC;
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unsigned Opc = 0;
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ISD::CondCode CC = ISD::SETCC_INVALID;
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switch (IntNo) {
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default: break;
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case Intrinsic::x86_sse_comieq_ss:
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@ -212,6 +212,14 @@ namespace llvm {
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/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
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bool isMOVHLPSMask(SDNode *N);
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/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
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bool isMOVLPMask(SDNode *N);
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/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}.
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bool isMOVHPMask(SDNode *N);
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/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to UNPCKL.
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bool isUNPCKLMask(SDNode *N);
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@ -96,6 +96,14 @@ def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVHLPSMask(N);
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}]>;
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def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVHPMask(N);
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}]>;
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def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVLPMask(N);
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}]>;
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def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKLMask(N);
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}]>;
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@ -712,17 +720,29 @@ def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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let isTwoAddress = 1 in {
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movlps {$src2, $dst|$dst, $src2}", []>;
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"movlps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVLP_shuffle_mask)))]>;
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def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movlpd {$src2, $dst|$dst, $src2}", []>;
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"movlpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)),
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MOVLP_shuffle_mask)))]>;
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def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movhps {$src2, $dst|$dst, $src2}", []>;
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"movhps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVHP_shuffle_mask)))]>;
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def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movhpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)),
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UNPCKL_shuffle_mask)))]>;
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MOVHP_shuffle_mask)))]>;
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}
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def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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@ -1706,6 +1726,8 @@ def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
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Requires<[HasSSE2]>;
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def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
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Requires<[HasSSE2]>;
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def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
|
||||
Requires<[HasSSE2]>;
|
||||
|
||||
// Zeroing a VR128 then do a MOVS* to the lower bits.
|
||||
def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
|
||||
|
Loading…
Reference in New Issue
Block a user