6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Modify operand order for Create{Sign,Zero}ExtensionInstructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3960 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2002-09-27 14:29:45 +00:00
parent 7e5167a3e2
commit 5cededee92
2 changed files with 21 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -497,10 +497,10 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
{ // sign- or zero-extend respectively
storeVal = new TmpInstruction(storeType, val);
if (val->getType()->isSigned())
CreateSignExtensionInstructions(target, F, val, 8*srcSize, storeVal,
CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
mvec, mcfi);
else
CreateZeroExtensionInstructions(target, F, val, 8*srcSize, storeVal,
CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
mvec, mcfi);
}
MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
@ -640,27 +640,27 @@ CreateBitExtensionInstructions(bool signExtend,
const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
Value* destVal,
unsigned int numLowBits,
vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi)
{
MachineInstr* M;
assert(srcSizeInBits <= 32 &&
"Hmmm... 32 < srcSizeInBits < 64 unexpected but could be handled.");
if (srcSizeInBits < 32)
assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
if (numLowBits < 32)
{ // SLL is needed since operand size is < 32 bits.
TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
srcVal, dest,"make32");
TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
srcVal, destVal, "make32");
mcfi.addTemp(tmpI);
M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-srcSizeInBits, tmpI);
M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-numLowBits, tmpI);
mvec.push_back(M);
srcVal = tmpI;
}
M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
srcVal, 32-srcSizeInBits, dest);
srcVal, 32-numLowBits, destVal);
mvec.push_back(M);
}
@ -676,13 +676,13 @@ UltraSparcInstrInfo::CreateSignExtensionInstructions(
const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
Value* destVal,
unsigned int numLowBits,
vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const
{
CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
srcSizeInBits, dest, mvec, mcfi);
destVal, numLowBits, mvec, mcfi);
}
@ -698,11 +698,11 @@ UltraSparcInstrInfo::CreateZeroExtensionInstructions(
const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
Value* destVal,
unsigned int numLowBits,
vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const
{
CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
srcSizeInBits, dest, mvec, mcfi);
destVal, numLowBits, mvec, mcfi);
}

8
lib/Target/SparcV9/SparcV9Internals.h
View File

@ -194,8 +194,8 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
virtual void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
Value* destVal,
unsigned int numLowBits,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const;
@ -208,8 +208,8 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
unsigned int srcSizeInBits,
Value* dest,
Value* destVal,
unsigned int numLowBits,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const;
};