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whatever. Intermediate patch to see what breaks. Seems ok.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24260 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-11-09 19:17:08 +00:00
parent 040c11c24e
commit 5cefc5e64d
8 changed files with 277 additions and 136 deletions
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4
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -50,8 +50,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setSetCCResultContents(ZeroOrOneSetCCResult);
addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);

59
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -786,8 +786,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
.addReg(argvregs[i]);
break;
case MVT::f32:
BuildMI(BB, Alpha::CPYSS, 2, args_float[i]).addReg(argvregs[i])
.addReg(argvregs[i]);
break;
case MVT::f64:
BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i])
BuildMI(BB, Alpha::CPYST, 2, args_float[i]).addReg(argvregs[i])
.addReg(argvregs[i]);
break;
}
@ -843,8 +846,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
break;
case MVT::f32:
case MVT::f64:
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
BuildMI(BB, Alpha::CPYSS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
break;
case MVT::f64:
BuildMI(BB, Alpha::CPYST, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
break;
}
return Result+N.ResNo;
@ -1039,10 +1044,17 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
Select(Chain);
unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
else
switch(N.getValue(0).getValueType()) {
case MVT::f32:
BuildMI(BB, Alpha::CPYSS, 2, Result).addReg(r).addReg(r);
break;
case MVT::f64:
BuildMI(BB, Alpha::CPYST, 2, Result).addReg(r).addReg(r);
break;
default:
BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
break;
}
return Result;
}
@ -1488,16 +1500,19 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
if(ISD::FABS == N.getOperand(0).getOpcode())
{
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS,
2, Result).addReg(Alpha::F31).addReg(Tmp1);
} else {
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS
, 2, Result).addReg(Tmp1).addReg(Tmp1);
}
return Result;
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYST : Alpha::CPYSS, 2, Result)
.addReg(Alpha::F31).addReg(Tmp1);
return Result;
case ISD::FP_ROUND:
@ -1519,10 +1534,12 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
case ISD::ConstantFP:
if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
if (CN->isExactlyValue(+0.0)) {
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYST : Alpha::CPYSS
, 2, Result).addReg(Alpha::F31)
.addReg(Alpha::F31);
} else if ( CN->isExactlyValue(-0.0)) {
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
BuildMI(BB, DestType == MVT::f64 ? Alpha::CPYSNT : Alpha::CPYSNS,
2, Result).addReg(Alpha::F31)
.addReg(Alpha::F31);
} else {
abort();
@ -1538,7 +1555,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
Tmp2 = MakeReg(MVT::f64);
MoveInt2FP(Tmp1, Tmp2, true);
Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2);
BuildMI(BB, Opc, 1, Result).addReg(Tmp2);
return Result;
}
@ -1605,11 +1622,17 @@ void AlphaISel::Select(SDOperand N) {
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
if (N.getOperand(2).getValueType() == MVT::f64 ||
N.getOperand(2).getValueType() == MVT::f32)
BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
else
switch(N.getOperand(2).getValueType()) {
case MVT::f64:
BuildMI(BB, Alpha::CPYST, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
break;
case MVT::f32:
BuildMI(BB, Alpha::CPYSS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
break;
default:
BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
break;
}
}
return;
@ -1629,8 +1652,10 @@ void AlphaISel::Select(SDOperand N) {
default: Node->dump();
assert(0 && "All other types should have been promoted!!");
case MVT::f64:
BuildMI(BB, Alpha::CPYST, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
break;
case MVT::f32:
BuildMI(BB, Alpha::CPYS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
BuildMI(BB, Alpha::CPYSS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
break;
case MVT::i32:
case MVT::i64:

34
lib/Target/Alpha/AlphaInstrFormats.td
View File

@ -26,17 +26,19 @@ def s64imm : Operand<i64>;
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction { // Alpha instruction baseline
// Alpha instruction baseline
class InstAlphaAlt<bits<6> op, string asmstr> : Instruction {
field bits<32> Inst;
let Namespace = "Alpha";
let OperandList = OL;
let AsmString = asmstr;
let Inst{31-26} = op;
}
class InstAlpha<bits<6> op, dag OL, string asmstr>
: InstAlphaAlt<op, asmstr> { // Alpha instruction baseline
let OperandList = OL;
}
//3.3.1
class MForm<bits<6> opcode, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
@ -92,7 +94,7 @@ class BFormD<bits<6> opcode, string asmstr>
let isBranch = 1, isTerminator = 1 in
class FBForm<bits<6> opcode, string asmstr>
: InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
: InstAlpha<opcode, (ops F8RC:$RA, s21imm:$DISP), asmstr> {
bits<5> Ra;
bits<21> disp;
@ -183,8 +185,10 @@ class OForm4L<bits<6> opcode, bits<7> fun, string asmstr>
}
//3.3.4
class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
: InstAlpha<opcode, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), asmstr> {
class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern>
: InstAlphaAlt<opcode, asmstr> {
let Pattern = pattern;
bits<5> Fc;
bits<5> Fa;
bits<5> Fb;
@ -196,20 +200,6 @@ class FPForm<bits<6> opcode, bits<11> fun, string asmstr>
let Inst{4-0} = Fc;
}
class FPFormCM<bits<6> opcode, bits<11> fun, string asmstr>
: InstAlpha<opcode, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), asmstr> {
bits<5> Fc;
bits<5> Fa;
bits<5> Fb;
bits<11> Function = fun;
let isTwoAddress = 1;
let Inst{25-21} = Fa;
let Inst{20-16} = Fb;
let Inst{15-5} = Function;
let Inst{4-0} = Fc;
}
//3.3.5
class PALForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
bits<26> Function;

4
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -26,7 +26,9 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
if (oc == Alpha::BIS || oc == Alpha::CPYS) { // or r1, r2, r2 // cpys r1 r2 r2
if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) {
// or r1, r2, r2
// cpys(s|t) r1 r2 r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&

185
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -96,19 +96,19 @@ def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
//really the ISel should emit multiple MBB
let isTwoAddress = 1 in {
//Conditional move of an int based on a FP CC
def CMOVEQ_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
def CMOVEQ_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"fbne $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
def CMOVEQi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, FPRC:$RCOND),
def CMOVEQi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
"fbne $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n">;
def CMOVNE_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
def CMOVNE_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"fbeq $RCOND, 42f\n\tbis $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
def CMOVNEi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, FPRC:$RCOND),
def CMOVNEi_FP : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, u8imm:$L, F8RC:$RCOND),
"fbeq $RCOND, 42f\n\taddq $$31,$L,$RDEST\n42:\n">;
//Conditional move of an FP based on a Int CC
def FCMOVEQ_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
def FCMOVEQ_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"bne $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
def FCMOVNE_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, FPRC:$RCOND),
def FCMOVNE_INT : PseudoInstAlpha<(ops GPRC:$RDEST, GPRC:$RSRC_F, GPRC:$RSRC_T, F8RC:$RCOND),
"beq $RCOND, 42f\n\tcpys $RSRC_T,$RSRC_T,$RDEST\n42:\n">;
}
@ -137,13 +137,15 @@ def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RC
def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
//conditional moves, fp
def FCMOVEQ : FPFormCM<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
def FCMOVGE : FPFormCM<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
def FCMOVGT : FPFormCM<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
def FCMOVLE : FPFormCM<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
def FCMOVLT : FPFormCM<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
def FCMOVNE : FPFormCM<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
isTwoAddress = 1 in {
def FCMOVEQ : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
def FCMOVGE : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
def FCMOVGT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
def FCMOVLE : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
def FCMOVLT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
def FCMOVNE : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
}
def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
[(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
@ -153,8 +155,6 @@ def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC",
[(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))]>;
def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC",
[(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))]>;
//def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture mask
//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask
def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC",
[(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))]>;
def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC",
@ -357,29 +357,6 @@ def : Pat<(setune GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
//Comparison, FP
def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal
def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than
def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
//There are in the Multimedia extentions, so let's not use them yet
//def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
//def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
//def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
//def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
//def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
//def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
//def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
//def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
//def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
//def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
//def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
//def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
//End operate
let isReturn = 1, isTerminator = 1 in
def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine
//DAG Version:
@ -488,67 +465,129 @@ def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero
def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
//Funky Floating point ops
def CPYS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC">; //Copy sign
def CPYSE : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC">; //Copy sign and exponent
def CPYSN : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC">; //Copy sign negate
//Basic Floating point ops
def ADDS : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC">; //Add S_floating
def ADDT : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC">; //Add T_floating
def SUBS : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC">; //Subtract S_floating
def SUBT : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC">; //Subtract T_floating
def DIVS : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC">; //Divide S_floating
def DIVT : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC">; //Divide T_floating
def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC">; //Multiply S_floating
def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC">; //Multiply T_floating
def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RA,$RB,$RC">; //Square root S_floating
def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RA,$RB,$RC">; //Square root T_floating
//INT reg to FP reg and back again
//not supported on 21164
def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC">; //Floating to integer move, S_floating
def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC">; //Floating to integer move, T_floating
def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC">; //Integer to floating move, S_floating
def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC">; //Integer to floating move, T_floating
//Floats
//CVTLQ F-P 17.010 Convert longword to quadword
//CVTQL F-P 17.030 Convert quadword to longword
//These use SW completion, may not have function code for that set right (matters for JIT)
def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC">; //Convert quadword to S_floating
def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC">; //Convert quadword to T_floating
def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC">; //Convert S_floating to T_floating
def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC">; //Convert T_floating to quadword
def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC">; //Convert T_floating to S_floating
let OperandList = (ops F4RC:$RC, F4RC:$RB), Fa = 31 in
def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RB,$RC",
[(set F4RC:$RC, (fsqrt F4RC:$RB))]>;
let OperandList = (ops F4RC:$RC, F4RC:$RA, F4RC:$RB) in {
def ADDS : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC",
[(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))]>;
def SUBS : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC",
[(set F4RC:$RC, (fsub F4RC:$RA, F4RC:$RB))]>;
def DIVS : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC",
[(set F4RC:$RC, (fdiv F4RC:$RA, F4RC:$RB))]>;
def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
[(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))]>;
def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
}
//Doubles
let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RB,$RC",
[(set F8RC:$RC, (fsqrt F8RC:$RB))]>;
let OperandList = (ops F8RC:$RC, F8RC:$RA, F8RC:$RB) in {
def ADDT : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC",
[(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))]>;
def SUBT : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC",
[(set F8RC:$RC, (fsub F8RC:$RA, F8RC:$RB))]>;
def DIVT : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC",
[(set F8RC:$RC, (fdiv F8RC:$RA, F8RC:$RB))]>;
def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
[(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))]>;
def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", []>;
// [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC", []>;
// [(set F8RC:$RC, (setle F8RC:$RA, F8RC:$RB))]>;
def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC", []>;
// [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>;
def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", []>;
// [(set F8RC:$RC, (setuo F8RC:$RA, F8RC:$RB))]>;
}
//TODO: Add lots more FP patterns
let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[]>; //Floating to integer move, S_floating
let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in
def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",[]>; //Floating to integer move, T_floating
let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in
def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[]>; //Integer to floating move, S_floating
let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in
def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",[]>; //Integer to floating move, T_floating
let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",[]>; //Convert quadword to S_floating
let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",[]>; //Convert quadword to T_floating
let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in
def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
[(set F8RC:$RC, (fextend F4RC:$RB))]>;
let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
[(set F4RC:$RC, (fround F8RC:$RB))]>;
//S_floating : IEEE Single
//T_floating : IEEE Double
//Unused instructions
//Mnemonic Format Opcode Description
//CALL_PAL Pcd 00 Trap to PALcode
//ECB Mfc 18.E800 Evict cache block
//EXCB Mfc 18.0400 Exception barrier
//FETCH Mfc 18.8000 Prefetch data
//FETCH_M Mfc 18.A000 Prefetch data, modify intent
//LDL_L Mem 2A Load sign-extended longword locked
//LDQ_L Mem 2B Load quadword locked
//LDQ_U Mem 0B Load unaligned quadword
//MB Mfc 18.4000 Memory barrier
//RPCC Mfc 18.C000 Read process cycle counter
//STL_C Mem 2E Store longword conditional
//STQ_C Mem 2F Store quadword conditional
//STQ_U Mem 0F Store unaligned quadword
//TRAPB Mfc 18.0000 Trap barrier
//WH64 Mfc 18.F800 Write hint  64 bytes
//WMB Mfc 18.4400 Write memory barrier
//MF_FPCR F-P 17.025 Move from FPCR
//MT_FPCR F-P 17.024 Move to FPCR
//There are in the Multimedia extentions, so let's not use them yet
//def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
//def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
//def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
//def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
//def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
//def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
//def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
//def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
//def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
//def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
//def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
//def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
//CVTLQ F-P 17.010 Convert longword to quadword
//CVTQL F-P 17.030 Convert quadword to longword
//def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture mask
//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask
def : Pat<(i64 immSExt16:$imm),
(LDA immSExt16:$imm, R31)>;

69
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -65,13 +65,6 @@ AlphaRegisterInfo::AlphaRegisterInfo()
{
}
static const TargetRegisterClass *getClass(unsigned SrcReg) {
if (Alpha::FPRCRegisterClass->contains(SrcReg))
return Alpha::FPRCRegisterClass;
assert(Alpha::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
return Alpha::GPRCRegisterClass;
}
void
AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
@ -82,9 +75,11 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(1)
.addImm(getUID());
if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@ -99,9 +94,11 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (EnableAlphaLSMark)
BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2)
.addImm(getUID());
if (getClass(DestReg) == Alpha::FPRCRegisterClass)
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (getClass(DestReg) == Alpha::GPRCRegisterClass)
else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@ -126,6 +123,50 @@ AlphaRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
return 0;
}
MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned OpNum,
int FrameIndex) const {
// Make sure this is a reg-reg copy.
unsigned Opc = MI->getOpcode();
if ((Opc == Alpha::BIS &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return BuildMI(Alpha::STQ, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
return BuildMI(Alpha::LDQ, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
} else if ((Opc == Alpha::CPYSS &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return BuildMI(Alpha::STS, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
return BuildMI(Alpha::LDS, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
} else if ((Opc == Alpha::CPYST &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return BuildMI(Alpha::STT, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
return BuildMI(Alpha::LDT, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
}
return 0;
}
void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
@ -133,8 +174,10 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
// std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (RC == Alpha::GPRCRegisterClass) {
BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == Alpha::FPRCRegisterClass) {
BuildMI(MBB, MI, Alpha::CPYS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == Alpha::F4RCRegisterClass) {
BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == Alpha::F8RCRegisterClass) {
BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();

3
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -37,6 +37,9 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
MachineInstr* foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
int FrameIndex) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;

55
lib/Target/Alpha/AlphaRegisterInfo.td
View File

@ -82,20 +82,59 @@ def F30 : FPR<30, "$f30">; def F31 : FPR<31, "$f31">;
def GPRC : RegisterClass<"Alpha", i64, 64,
// Volatile
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
R23, R24, R25,
R23, R24, R25, R28,
//Special meaning, but volatile
R27, //procedure address
R26, //return address
R29, //global offset table address
// Non-volatile
R9, R10, R11, R12, R13, R14 ]>;
// Note: R28 is reserved for the assembler
R9, R10, R11, R12, R13, R14,
R31 ]> //zero
{
let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const;
}];
let MethodBodies = [{
GPRCClass::iterator
GPRCClass::allocation_order_end(MachineFunction &MF) const {
return end()-1;
}
}];
}
// Don't allocate 15, 29, 30, 31
// Allocation volatiles only for now
def FPRC : RegisterClass<"Alpha", f64, 64, [F0, F1,
def F4RC : RegisterClass<"Alpha", f32, 64, [F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
// Saved:
F2, F3, F4, F5, F6, F7, F8, F9
]>;
F2, F3, F4, F5, F6, F7, F8, F9,
F31 ]> //zero
{
let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const;
}];
let MethodBodies = [{
F4RCClass::iterator
F4RCClass::allocation_order_end(MachineFunction &MF) const {
return end()-1;
}
}];
}
def F8RC : RegisterClass<"Alpha", f64, 64, [F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
// Saved:
F2, F3, F4, F5, F6, F7, F8, F9,
F31 ]> //zero
{
let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const;
}];
let MethodBodies = [{
F8RCClass::iterator
F8RCClass::allocation_order_end(MachineFunction &MF) const {
return end()-1;
}
}];
}