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Get rid of some unnecessary code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73017 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2009-06-07 07:28:45 +00:00
parent a5f54a06b0
commit 5d28eb9e97
1 changed files with 0 additions and 25 deletions
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25
lib/Target/X86/X86ISelLowering.cpp
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@ -7743,31 +7743,6 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
if (VT.getSizeInBits() != 128)
return SDValue();
// For x86-32 machines, if we see an insert and then a shuffle in a v2i64
// where the upper half is 0, it is advantageous to rewrite it as a build
// vector of (0, val) so it can use movq.
if (VT == MVT::v2i64) {
SDValue In[2];
In[0] = N->getOperand(0);
In[1] = N->getOperand(1);
int Idx0 = SVN->getMaskElt(0);
int Idx1 = SVN->getMaskElt(1);
// FIXME: can we take advantage of undef index?
if (Idx0 >= 0 && Idx1 >= 0 &&
In[Idx0/2].getOpcode() == ISD::INSERT_VECTOR_ELT &&
In[Idx1/2].getOpcode() == ISD::BUILD_VECTOR) {
ConstantSDNode* InsertVecIdx =
dyn_cast<ConstantSDNode>(In[Idx0/2].getOperand(2));
if (InsertVecIdx &&
InsertVecIdx->getZExtValue() == (unsigned)(Idx0 % 2) &&
isZeroNode(In[Idx1/2].getOperand(Idx1 % 2))) {
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
In[Idx0/2].getOperand(1),
In[Idx1/2].getOperand(Idx1 % 2));
}
}
}
// Try to combine a vector_shuffle into a 128-bit load.
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
LoadSDNode *LD = NULL;