From 5d446265c740c17ed12e693423f0363296670d60 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Thu, 15 Nov 2007 08:13:29 +0000
Subject: [PATCH] Fix a thinko in post-allocation coalescer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44166 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/LiveIntervalAnalysis.cpp         | 13 +++-
 test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll | 67 ++++++++++++++++++++
 2 files changed, 77 insertions(+), 3 deletions(-)
 create mode 100644 test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 833868a4585..55094e3e5d6 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -168,15 +168,22 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
       if (index == end) break;
 
       MachineInstr *MI = getInstructionFromIndex(index);
+      unsigned SrcReg, DstReg;
+      if (tii_->isMoveInstr(*MI, SrcReg, DstReg))
+        if (SrcReg == li.reg || DstReg == li.reg)
+          continue;
       for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
         MachineOperand& mop = MI->getOperand(i);
-        if (!mop.isRegister() || !mop.isDef())
+        if (!mop.isRegister())
           continue;
         unsigned PhysReg = mop.getReg();
-        if (PhysReg == 0)
+        if (PhysReg == 0 || PhysReg == li.reg)
           continue;
-        if (MRegisterInfo::isVirtualRegister(PhysReg))
+        if (MRegisterInfo::isVirtualRegister(PhysReg)) {
+          if (!vrm.hasPhys(PhysReg))
+            continue;
           PhysReg = vrm.getPhys(PhysReg);
+        }
         if (PhysReg && mri_->regsOverlap(PhysReg, reg))
           return true;
       }
diff --git a/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll b/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
new file mode 100644
index 00000000000..4a8f37608b5
--- /dev/null
+++ b/test/CodeGen/X86/2007-11-14-Coalescer-Bug.ll
@@ -0,0 +1,67 @@
+; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=att | grep movl | grep 4
+
+	%struct.double_int = type { i64, i64 }
+	%struct.tree_common = type <{ i8, [3 x i8] }>
+	%struct.tree_int_cst = type { %struct.tree_common, %struct.double_int }
+	%struct.tree_node = type { %struct.tree_int_cst }
+@tree_code_type = external constant [0 x i32]		; <[0 x i32]*> [#uses=1]
+
+define i32 @simple_cst_equal(%struct.tree_node* %t1, %struct.tree_node* %t2) {
+entry:
+	%tmp2526 = bitcast %struct.tree_node* %t1 to i32*		; <i32*> [#uses=1]
+	br i1 false, label %UnifiedReturnBlock, label %bb21
+
+bb21:		; preds = %entry
+	%tmp27 = load i32* %tmp2526, align 4		; <i32> [#uses=1]
+	%tmp29 = and i32 %tmp27, 255		; <i32> [#uses=3]
+	%tmp2930 = trunc i32 %tmp29 to i8		; <i8> [#uses=1]
+	%tmp37 = load i32* null, align 4		; <i32> [#uses=1]
+	%tmp39 = and i32 %tmp37, 255		; <i32> [#uses=2]
+	%tmp3940 = trunc i32 %tmp39 to i8		; <i8> [#uses=1]
+	%tmp43 = add i32 %tmp29, -3		; <i32> [#uses=1]
+	%tmp44 = icmp ult i32 %tmp43, 3		; <i1> [#uses=1]
+	br i1 %tmp44, label %bb47.split, label %bb76
+
+bb47.split:		; preds = %bb21
+	ret i32 0
+
+bb76:		; preds = %bb21
+	br i1 false, label %bb82, label %bb146.split
+
+bb82:		; preds = %bb76
+	%tmp94 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp39		; <i32*> [#uses=1]
+	%tmp95 = load i32* %tmp94, align 4		; <i32> [#uses=1]
+	%tmp9596 = trunc i32 %tmp95 to i8		; <i8> [#uses=1]
+	%tmp98 = add i8 %tmp9596, -4		; <i8> [#uses=1]
+	%tmp99 = icmp ugt i8 %tmp98, 5		; <i1> [#uses=1]
+	br i1 %tmp99, label %bb102, label %bb106
+
+bb102:		; preds = %bb82
+	ret i32 0
+
+bb106:		; preds = %bb82
+	ret i32 0
+
+bb146.split:		; preds = %bb76
+	%tmp149 = icmp eq i8 %tmp2930, %tmp3940		; <i1> [#uses=1]
+	br i1 %tmp149, label %bb153, label %UnifiedReturnBlock
+
+bb153:		; preds = %bb146.split
+	switch i32 %tmp29, label %UnifiedReturnBlock [
+		 i32 0, label %bb155
+		 i32 1, label %bb187
+	]
+
+bb155:		; preds = %bb153
+	ret i32 0
+
+bb187:		; preds = %bb153
+	%tmp198 = icmp eq %struct.tree_node* %t1, %t2		; <i1> [#uses=1]
+	br i1 %tmp198, label %bb201, label %UnifiedReturnBlock
+
+bb201:		; preds = %bb187
+	ret i32 0
+
+UnifiedReturnBlock:		; preds = %bb187, %bb153, %bb146.split, %entry
+	ret i32 0
+}