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Update Cortex-A8 instruction itineraries for integer instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Goodwin 2009-08-19 18:00:44 +00:00
parent e0c951a5af
commit 5d598aaf3d
6 changed files with 650 additions and 365 deletions

249
lib/Target/ARM/ARMInstrInfo.td

@ -344,18 +344,18 @@ include "ARMInstrFormats.td"
multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode, multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> { bit Commutable = 0> {
def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALU, opc, " $dst, $a, $b", IIC_iALUi, opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> { [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
let Inst{25} = 1; let Inst{25} = 1;
} }
def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
IIC_iALU, opc, " $dst, $a, $b", IIC_iALUr, opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> { [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
let Inst{25} = 0; let Inst{25} = 0;
let isCommutable = Commutable; let isCommutable = Commutable;
} }
def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALU, opc, " $dst, $a, $b", IIC_iALUsr, opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> { [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
let Inst{25} = 0; let Inst{25} = 0;
} }
@ -367,18 +367,18 @@ let Defs = [CPSR] in {
multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode, multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> { bit Commutable = 0> {
def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALU, opc, "s $dst, $a, $b", IIC_iALUi, opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> { [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
let Inst{25} = 1; let Inst{25} = 1;
} }
def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
IIC_iALU, opc, "s $dst, $a, $b", IIC_iALUr, opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> { [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
let Inst{25} = 0; let Inst{25} = 0;
} }
def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALU, opc, "s $dst, $a, $b", IIC_iALUsr, opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> { [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
let Inst{25} = 0; let Inst{25} = 0;
} }
@ -391,18 +391,18 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
let Defs = [CPSR] in { let Defs = [CPSR] in {
multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode, multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> { bit Commutable = 0> {
def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iALU, def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
opc, " $a, $b", opc, " $a, $b",
[(opnode GPR:$a, so_imm:$b)]> { [(opnode GPR:$a, so_imm:$b)]> {
let Inst{25} = 1; let Inst{25} = 1;
} }
def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALU, def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
opc, " $a, $b", opc, " $a, $b",
[(opnode GPR:$a, GPR:$b)]> { [(opnode GPR:$a, GPR:$b)]> {
let Inst{25} = 0; let Inst{25} = 0;
let isCommutable = Commutable; let isCommutable = Commutable;
} }
def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iALU, def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
opc, " $a, $b", opc, " $a, $b",
[(opnode GPR:$a, so_reg:$b)]> { [(opnode GPR:$a, so_reg:$b)]> {
let Inst{25} = 0; let Inst{25} = 0;
@ -414,15 +414,15 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
/// FIXME: Remove the 'r' variant. Its rot_imm is zero. /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> { multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src), def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
IIC_iALU, opc, " $dst, $Src", IIC_iUNAr, opc, " $dst, $src",
[(set GPR:$dst, (opnode GPR:$Src))]>, [(set GPR:$dst, (opnode GPR:$src))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
let Inst{19-16} = 0b1111; let Inst{19-16} = 0b1111;
} }
def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
IIC_iALU, opc, " $dst, $Src, ror $rot", IIC_iUNAsi, opc, " $dst, $src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
let Inst{19-16} = 0b1111; let Inst{19-16} = 0b1111;
} }
@ -432,11 +432,11 @@ multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> { multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
IIC_iALU, opc, " $dst, $LHS, $RHS", IIC_iALUr, opc, " $dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
IIC_iALU, opc, " $dst, $LHS, $RHS, ror $rot", IIC_iALUsi, opc, " $dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS, [(set GPR:$dst, (opnode GPR:$LHS,
(rotr GPR:$RHS, rot_imm:$rot)))]>, (rotr GPR:$RHS, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
@ -447,41 +447,41 @@ let Uses = [CPSR] in {
multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> { bit Commutable = 0> {
def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALU, opc, " $dst, $a, $b", DPFrm, IIC_iALUi, opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
Requires<[IsARM, CarryDefIsUnused]> { Requires<[IsARM, CarryDefIsUnused]> {
let Inst{25} = 1; let Inst{25} = 1;
} }
def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
DPFrm, IIC_iALU, opc, " $dst, $a, $b", DPFrm, IIC_iALUr, opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
Requires<[IsARM, CarryDefIsUnused]> { Requires<[IsARM, CarryDefIsUnused]> {
let isCommutable = Commutable; let isCommutable = Commutable;
let Inst{25} = 0; let Inst{25} = 0;
} }
def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALU, opc, " $dst, $a, $b", DPSoRegFrm, IIC_iALUsr, opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
Requires<[IsARM, CarryDefIsUnused]> { Requires<[IsARM, CarryDefIsUnused]> {
let Inst{25} = 0; let Inst{25} = 0;
} }
// Carry setting variants // Carry setting variants
def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALU, !strconcat(opc, "s $dst, $a, $b"), DPFrm, IIC_iALUi, !strconcat(opc, "s $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
Requires<[IsARM, CarryDefIsUsed]> { Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR]; let Defs = [CPSR];
let Inst{25} = 1; let Inst{25} = 1;
} }
def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
DPFrm, IIC_iALU, !strconcat(opc, "s $dst, $a, $b"), DPFrm, IIC_iALUr, !strconcat(opc, "s $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
Requires<[IsARM, CarryDefIsUsed]> { Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR]; let Defs = [CPSR];
let Inst{25} = 0; let Inst{25} = 0;
} }
def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALU, !strconcat(opc, "s $dst, $a, $b"), DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
Requires<[IsARM, CarryDefIsUsed]> { Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR]; let Defs = [CPSR];
@ -529,42 +529,42 @@ PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
// Address computation and loads and stores in PIC mode. // Address computation and loads and stores in PIC mode.
let isNotDuplicable = 1 in { let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
Pseudo, IIC_iALU, "$cp:\n\tadd$p $dst, pc, $a", Pseudo, IIC_iALUr, "$cp:\n\tadd$p $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
let AddedComplexity = 10 in { let AddedComplexity = 10 in {
let canFoldAsLoad = 1 in let canFoldAsLoad = 1 in
def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad, "${addr:label}:\n\tldr$p $dst, $addr", Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>; [(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}h $dst, $addr", Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}b $dst, $addr", Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}sh $dst, $addr", Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad, "${addr:label}:\n\tldr${p}sb $dst, $addr", Pseudo, IIC_iLoadr, "${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
} }
let AddedComplexity = 10 in { let AddedComplexity = 10 in {
def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStore, "${addr:label}:\n\tstr$p $src, $addr", Pseudo, IIC_iStorer, "${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>; [(store GPR:$src, addrmodepc:$addr)]>;
def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStore, "${addr:label}:\n\tstr${p}h $src, $addr", Pseudo, IIC_iStorer, "${addr:label}:\n\tstr${p}h $src, $addr",
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>; [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, IIC_iStore, "${addr:label}:\n\tstr${p}b $src, $addr", Pseudo, IIC_iStorer, "${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>; [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
} }
} // isNotDuplicable = 1 } // isNotDuplicable = 1
@ -573,7 +573,7 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// LEApcrel - Load a pc-relative address into a register without offending the // LEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.
def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
Pseudo, IIC_iLoad, Pseudo, IIC_iALUi,
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(", !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+8))\n"), "${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t", !strconcat("${:private}PCRELL${:uid}:\n\t",
@ -582,7 +582,7 @@ def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
(ins i32imm:$label, lane_cst:$id, pred:$p), (ins i32imm:$label, lane_cst:$id, pred:$p),
Pseudo, IIC_iLoad, Pseudo, IIC_iALUi,
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, " !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
"(${label}_${id}-(", "(${label}_${id}-(",
"${:private}PCRELL${:uid}+8))\n"), "${:private}PCRELL${:uid}+8))\n"),
@ -736,139 +736,140 @@ let isBranch = 1, isTerminator = 1 in {
// Load // Load
let canFoldAsLoad = 1 in let canFoldAsLoad = 1 in
def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad, def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
"ldr", " $dst, $addr", "ldr", " $dst, $addr",
[(set GPR:$dst, (load addrmode2:$addr))]>; [(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools. // Special LDR for loads from non-pc-relative constpools.
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad, def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
"ldr", " $dst, $addr", []>; "ldr", " $dst, $addr", []>;
// Loads with zero extension // Loads with zero extension
def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad, def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "h $dst, $addr", IIC_iLoadr, "ldr", "h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoad, def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", "b $dst, $addr", IIC_iLoadr, "ldr", "b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
// Loads with sign extension // Loads with sign extension
def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad, def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "sh $dst, $addr", IIC_iLoadr, "ldr", "sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad, def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "sb $dst, $addr", IIC_iLoadr, "ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
let mayLoad = 1 in { let mayLoad = 1 in {
// Load doubleword // Load doubleword
def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad, "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>; IIC_iLoadr, "ldr", "d $dst1, $addr",
[]>, Requires<[IsARM, HasV5T]>;
// Indexed loads // Indexed loads
def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad, (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
"ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad, (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad, (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad, (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad, (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
"ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad, (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad, (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad, (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad, (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad, (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
} }
// Store // Store
def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore, def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
"str", " $src, $addr", "str", " $src, $addr",
[(store GPR:$src, addrmode2:$addr)]>; [(store GPR:$src, addrmode2:$addr)]>;
// Stores with truncate // Stores with truncate
def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStore, def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
"str", "h $src, $addr", "str", "h $src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>; [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore, def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
"str", "b $src, $addr", "str", "b $src, $addr",
[(truncstorei8 GPR:$src, addrmode2:$addr)]>; [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword // Store doubleword
let mayStore = 1 in let mayStore = 1 in
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
StMiscFrm, IIC_iStore, StMiscFrm, IIC_iStorer,
"str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>; "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
// Indexed stores // Indexed stores
def STR_PRE : AI2stwpr<(outs GPR:$base_wb), def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, am2offset:$offset), (ins GPR:$src, GPR:$base, am2offset:$offset),
StFrm, IIC_iStore, StFrm, IIC_iStoreru,
"str", " $src, [$base, $offset]!", "$base = $base_wb", "str", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
def STR_POST : AI2stwpo<(outs GPR:$base_wb), def STR_POST : AI2stwpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore, StFrm, IIC_iStoreru,
"str", " $src, [$base], $offset", "$base = $base_wb", "str", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>; (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset), (ins GPR:$src, GPR:$base,am3offset:$offset),
StMiscFrm, IIC_iStore, StMiscFrm, IIC_iStoreru,
"str", "h $src, [$base, $offset]!", "$base = $base_wb", "str", "h $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
def STRH_POST: AI3sthpo<(outs GPR:$base_wb), def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset), (ins GPR:$src, GPR:$base,am3offset:$offset),
StMiscFrm, IIC_iStore, StMiscFrm, IIC_iStoreru,
"str", "h $src, [$base], $offset", "$base = $base_wb", "str", "h $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti16 GPR:$src, [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
GPR:$base, am3offset:$offset))]>; GPR:$base, am3offset:$offset))]>;
def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore, StFrm, IIC_iStoreru,
"str", "b $src, [$base, $offset]!", "$base = $base_wb", "str", "b $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src, [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>; GPR:$base, am2offset:$offset))]>;
def STRB_POST: AI2stbpo<(outs GPR:$base_wb), def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), (ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore, StFrm, IIC_iStoreru,
"str", "b $src, [$base], $offset", "$base = $base_wb", "str", "b $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti8 GPR:$src, [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>; GPR:$base, am2offset:$offset))]>;
@ -881,13 +882,13 @@ def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
let mayLoad = 1 in let mayLoad = 1 in
def LDM : AXI4ld<(outs), def LDM : AXI4ld<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdStMulFrm, IIC_iLoad, "ldm${p}${addr:submode} $addr, $dst1", LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $dst1",
[]>; []>;
let mayStore = 1 in let mayStore = 1 in
def STM : AXI4st<(outs), def STM : AXI4st<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
LdStMulFrm, IIC_iStore, "stm${p}${addr:submode} $addr, $src1", LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $src1",
[]>; []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -895,17 +896,17 @@ def STM : AXI4st<(outs),
// //
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iALU, def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
"mov", " $dst, $src", []>, UnaryDP; "mov", " $dst, $src", []>, UnaryDP;
def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
DPSoRegFrm, IIC_iALU, DPSoRegFrm, IIC_iMOVsr,
"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP; "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iALU, def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP; "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iALU, def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
"mov", " $dst, $src, rrx", "mov", " $dst, $src, rrx",
[(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
@ -914,10 +915,10 @@ def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iALU,
let Defs = [CPSR] in { let Defs = [CPSR] in {
def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
IIC_iALU, "mov", "s $dst, $src, lsr #1", IIC_iMOVsi, "mov", "s $dst, $src, lsr #1",
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP; [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
IIC_iALU, "mov", "s $dst, $src, asr #1", IIC_iMOVsi, "mov", "s $dst, $src, asr #1",
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP; [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
} }
@ -987,30 +988,30 @@ defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
// These don't define reg/reg forms, because they are handled above. // These don't define reg/reg forms, because they are handled above.
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALU, "rsb", " $dst, $a, $b", IIC_iALUi, "rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALU, "rsb", " $dst, $a, $b", IIC_iALUsr, "rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
// RSB with 's' bit set. // RSB with 's' bit set.
let Defs = [CPSR] in { let Defs = [CPSR] in {
def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALU, "rsb", "s $dst, $a, $b", IIC_iALUi, "rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALU, "rsb", "s $dst, $a, $b", IIC_iALUsr, "rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
} }
let Uses = [CPSR] in { let Uses = [CPSR] in {
def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALU, "rsc", " $dst, $a, $b", DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]>; Requires<[IsARM, CarryDefIsUnused]>;
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALU, "rsc", " $dst, $a, $b", DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]>; Requires<[IsARM, CarryDefIsUnused]>;
} }
@ -1018,11 +1019,11 @@ def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
// FIXME: Allow these to be predicated. // FIXME: Allow these to be predicated.
let Defs = [CPSR], Uses = [CPSR] in { let Defs = [CPSR], Uses = [CPSR] in {
def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
DPFrm, IIC_iALU, "rscs $dst, $a, $b", DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]>; Requires<[IsARM, CarryDefIsUnused]>;
def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALU, "rscs $dst, $a, $b", DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]>; Requires<[IsARM, CarryDefIsUnused]>;
} }
@ -1057,7 +1058,7 @@ defm BIC : AsI1_bin_irs<0b1110, "bic",
BinOpFrag<(and node:$LHS, (not node:$RHS))>>; BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALU, AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
"bfc", " $dst, $imm", "$src = $dst", "bfc", " $dst, $imm", "$src = $dst",
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>, [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
Requires<[IsARM, HasV6T2]> { Requires<[IsARM, HasV6T2]> {
@ -1065,15 +1066,15 @@ def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
let Inst{6-0} = 0b0011111; let Inst{6-0} = 0b0011111;
} }
def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iALU, def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
"mvn", " $dst, $src", "mvn", " $dst, $src",
[(set GPR:$dst, (not GPR:$src))]>, UnaryDP; [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
IIC_iALU, "mvn", " $dst, $src", IIC_iMOVsr, "mvn", " $dst, $src",
[(set GPR:$dst, (not so_reg:$src))]>, UnaryDP; [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, IIC_iALU, def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
"mvn", " $dst, $imm", IIC_iMOVi, "mvn", " $dst, $imm",
[(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP; [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
def : ARMPat<(and GPR:$src, so_imm_not:$imm), def : ARMPat<(and GPR:$src, so_imm_not:$imm),
@ -1084,16 +1085,16 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm),
// //
let isCommutable = 1 in let isCommutable = 1 in
def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
"mul", " $dst, $a, $b", IIC_iMUL32, "mul", " $dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMPYw, "mla", " $dst, $a, $b, $c", IIC_iMAC32, "mla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMPYw, "mls", " $dst, $a, $b, $c", IIC_iMAC32, "mls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>, [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
Requires<[IsARM, HasV6T2]>; Requires<[IsARM, HasV6T2]>;
@ -1101,32 +1102,32 @@ def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
let isCommutable = 1 in { let isCommutable = 1 in {
def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst), def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
(ins GPR:$a, GPR:$b), IIC_iMPYl, (ins GPR:$a, GPR:$b), IIC_iMUL64,
"smull", " $ldst, $hdst, $a, $b", []>; "smull", " $ldst, $hdst, $a, $b", []>;
def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst), def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
(ins GPR:$a, GPR:$b), IIC_iMPYl, (ins GPR:$a, GPR:$b), IIC_iMUL64,
"umull", " $ldst, $hdst, $a, $b", []>; "umull", " $ldst, $hdst, $a, $b", []>;
} }
// Multiply + accumulate // Multiply + accumulate
def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst), def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
(ins GPR:$a, GPR:$b), IIC_iMPYl, (ins GPR:$a, GPR:$b), IIC_iMAC64,
"smlal", " $ldst, $hdst, $a, $b", []>; "smlal", " $ldst, $hdst, $a, $b", []>;
def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst), def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
(ins GPR:$a, GPR:$b), IIC_iMPYl, (ins GPR:$a, GPR:$b), IIC_iMAC64,
"umlal", " $ldst, $hdst, $a, $b", []>; "umlal", " $ldst, $hdst, $a, $b", []>;
def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst), def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
(ins GPR:$a, GPR:$b), IIC_iMPYl, (ins GPR:$a, GPR:$b), IIC_iMAC64,
"umaal", " $ldst, $hdst, $a, $b", []>, "umaal", " $ldst, $hdst, $a, $b", []>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
} // neverHasSideEffects } // neverHasSideEffects
// Most significant word multiply // Most significant word multiply
def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYw, "smmul", " $dst, $a, $b", IIC_iMUL32, "smmul", " $dst, $a, $b",
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0001; let Inst{7-4} = 0b0001;
@ -1134,7 +1135,7 @@ def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
} }
def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMPYw, "smmla", " $dst, $a, $b, $c", IIC_iMAC32, "smmla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0001; let Inst{7-4} = 0b0001;
@ -1142,7 +1143,7 @@ def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
IIC_iMPYw, "smmls", " $dst, $a, $b, $c", IIC_iMAC32, "smmls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b1101; let Inst{7-4} = 0b1101;
@ -1150,7 +1151,7 @@ def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
multiclass AI_smul<string opc, PatFrag opnode> { multiclass AI_smul<string opc, PatFrag opnode> {
def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYw, !strconcat(opc, "bb"), " $dst, $a, $b", IIC_iMUL32, !strconcat(opc, "bb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16)))]>, (sext_inreg GPR:$b, i16)))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1159,7 +1160,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
} }
def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYw, !strconcat(opc, "bt"), " $dst, $a, $b", IIC_iMUL32, !strconcat(opc, "bt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, (i32 16))))]>, (sra GPR:$b, (i32 16))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1168,7 +1169,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
} }
def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYw, !strconcat(opc, "tb"), " $dst, $a, $b", IIC_iMUL32, !strconcat(opc, "tb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
(sext_inreg GPR:$b, i16)))]>, (sext_inreg GPR:$b, i16)))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1177,7 +1178,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
} }
def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYw, !strconcat(opc, "tt"), " $dst, $a, $b", IIC_iMUL32, !strconcat(opc, "tt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
(sra GPR:$b, (i32 16))))]>, (sra GPR:$b, (i32 16))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1186,7 +1187,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
} }
def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYh, !strconcat(opc, "wb"), " $dst, $a, $b", IIC_iMUL16, !strconcat(opc, "wb"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a, [(set GPR:$dst, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), (i32 16)))]>, (sext_inreg GPR:$b, i16)), (i32 16)))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1195,7 +1196,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
} }
def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
IIC_iMPYh, !strconcat(opc, "wt"), " $dst, $a, $b", IIC_iMUL16, !strconcat(opc, "wt"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a, [(set GPR:$dst, (sra (opnode GPR:$a,
(sra GPR:$b, (i32 16))), (i32 16)))]>, (sra GPR:$b, (i32 16))), (i32 16)))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1207,7 +1208,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
multiclass AI_smla<string opc, PatFrag opnode> { multiclass AI_smla<string opc, PatFrag opnode> {
def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
IIC_iMPYw, !strconcat(opc, "bb"), " $dst, $a, $b, $acc", IIC_iMAC16, !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, [(set GPR:$dst, (add GPR:$acc,
(opnode (sext_inreg GPR:$a, i16), (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16))))]>, (sext_inreg GPR:$b, i16))))]>,
@ -1217,7 +1218,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
} }
def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
IIC_iMPYw, !strconcat(opc, "bt"), " $dst, $a, $b, $acc", IIC_iMAC16, !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, (i32 16)))))]>, (sra GPR:$b, (i32 16)))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1226,7 +1227,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
} }
def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
IIC_iMPYw, !strconcat(opc, "tb"), " $dst, $a, $b, $acc", IIC_iMAC16, !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
(sext_inreg GPR:$b, i16))))]>, (sext_inreg GPR:$b, i16))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1235,7 +1236,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
} }
def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
IIC_iMPYw, !strconcat(opc, "tt"), " $dst, $a, $b, $acc", IIC_iMAC16, !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
(sra GPR:$b, (i32 16)))))]>, (sra GPR:$b, (i32 16)))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1244,7 +1245,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
} }
def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
IIC_iMPYw, !strconcat(opc, "wb"), " $dst, $a, $b, $acc", IIC_iMAC16, !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), (i32 16))))]>, (sext_inreg GPR:$b, i16)), (i32 16))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1253,7 +1254,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
} }
def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
IIC_iMPYw, !strconcat(opc, "wt"), " $dst, $a, $b, $acc", IIC_iMAC16, !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sra GPR:$b, (i32 16))), (i32 16))))]>, (sra GPR:$b, (i32 16))), (i32 16))))]>,
Requires<[IsARM, HasV5TE]> { Requires<[IsARM, HasV5TE]> {
@ -1272,7 +1273,7 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
// Misc. Arithmetic Instructions. // Misc. Arithmetic Instructions.
// //
def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iALU, def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"clz", " $dst, $src", "clz", " $dst, $src",
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> { [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
let Inst{7-4} = 0b0001; let Inst{7-4} = 0b0001;
@ -1280,7 +1281,7 @@ def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
let Inst{19-16} = 0b1111; let Inst{19-16} = 0b1111;
} }
def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iALU, def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"rev", " $dst, $src", "rev", " $dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> { [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
let Inst{7-4} = 0b0011; let Inst{7-4} = 0b0011;
@ -1288,7 +1289,7 @@ def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
let Inst{19-16} = 0b1111; let Inst{19-16} = 0b1111;
} }
def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iALU, def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"rev16", " $dst, $src", "rev16", " $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(or (and (srl GPR:$src, (i32 8)), 0xFF), (or (and (srl GPR:$src, (i32 8)), 0xFF),
@ -1301,7 +1302,7 @@ def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
let Inst{19-16} = 0b1111; let Inst{19-16} = 0b1111;
} }
def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iALU, def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"revsh", " $dst, $src", "revsh", " $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(sext_inreg (sext_inreg
@ -1315,7 +1316,7 @@ def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iALU,
def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst), def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
(ins GPR:$src1, GPR:$src2, i32imm:$shamt), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
IIC_iALU, "pkhbt", " $dst, $src1, $src2, LSL $shamt", IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
(and (shl GPR:$src2, (i32 imm:$shamt)), (and (shl GPR:$src2, (i32 imm:$shamt)),
0xFFFF0000)))]>, 0xFFFF0000)))]>,
@ -1332,7 +1333,7 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
(ins GPR:$src1, GPR:$src2, i32imm:$shamt), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
IIC_iALU, "pkhtb", " $dst, $src1, $src2, ASR $shamt", IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
(and (sra GPR:$src2, imm16_31:$shamt), (and (sra GPR:$src2, imm16_31:$shamt),
0xFFFF)))]>, Requires<[IsARM, HasV6]> { 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
@ -1378,18 +1379,18 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
IIC_iALU, "mov", " $dst, $true", IIC_iCMOVr, "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP; RegConstraint<"$false = $dst">, UnaryDP;
def MOVCCs : AI1<0b1101, (outs GPR:$dst), def MOVCCs : AI1<0b1101, (outs GPR:$dst),
(ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iALU, (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
"mov", " $dst, $true", "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP; RegConstraint<"$false = $dst">, UnaryDP;
def MOVCCi : AI1<0b1101, (outs GPR:$dst), def MOVCCi : AI1<0b1101, (outs GPR:$dst),
(ins GPR:$false, so_imm:$true), DPFrm, IIC_iALU, (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
"mov", " $dst, $true", "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP; RegConstraint<"$false = $dst">, UnaryDP;
@ -1451,7 +1452,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
// Two piece so_imms. // Two piece so_imms.
let isReMaterializable = 1 in let isReMaterializable = 1 in
def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
Pseudo, IIC_iALU, Pseudo, IIC_iMOVi,
"mov", " $dst, $src", "mov", " $dst, $src",
[(set GPR:$dst, so_imm2part:$src)]>; [(set GPR:$dst, so_imm2part:$src)]>;

144
lib/Target/ARM/ARMInstrThumb.td

@ -129,32 +129,32 @@ PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
// For both thumb1 and thumb2. // For both thumb1 and thumb2.
let isNotDuplicable = 1 in let isNotDuplicable = 1 in
def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALU, def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
"$cp:\n\tadd $dst, pc", "$cp:\n\tadd $dst, pc",
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
// PC relative add. // PC relative add.
def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALU, def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi,
"add $dst, pc, $rhs * 4", []>; "add $dst, pc, $rhs * 4", []>;
// ADD rd, sp, #imm8 // ADD rd, sp, #imm8
def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALU, def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi,
"add $dst, $sp, $rhs * 4 @ addrspi", []>; "add $dst, $sp, $rhs * 4 @ addrspi", []>;
// ADD sp, sp, #imm7 // ADD sp, sp, #imm7
def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU, def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
"add $dst, $rhs * 4", []>; "add $dst, $rhs * 4", []>;
// SUB sp, sp, #imm7 // SUB sp, sp, #imm7
def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU, def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
"sub $dst, $rhs * 4", []>; "sub $dst, $rhs * 4", []>;
// ADD rm, sp // ADD rm, sp
def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
"add $dst, $rhs", []>; "add $dst, $rhs", []>;
// ADD sp, rm // ADD sp, rm
def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
"add $dst, $rhs", []>; "add $dst, $rhs", []>;
// Pseudo instruction that will expand into a tSUBspi + a copy. // Pseudo instruction that will expand into a tSUBspi + a copy.
@ -276,71 +276,71 @@ let isBranch = 1, isTerminator = 1 in
// //
let canFoldAsLoad = 1 in let canFoldAsLoad = 1 in
def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad, def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
"ldr", " $dst, $addr", "ldr", " $dst, $addr",
[(set tGPR:$dst, (load t_addrmode_s4:$addr))]>; [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad, def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
"ldrb", " $dst, $addr", "ldrb", " $dst, $addr",
[(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>; [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad, def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
"ldrh", " $dst, $addr", "ldrh", " $dst, $addr",
[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>; [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
let AddedComplexity = 10 in let AddedComplexity = 10 in
def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad, def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
"ldrsb", " $dst, $addr", "ldrsb", " $dst, $addr",
[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
let AddedComplexity = 10 in let AddedComplexity = 10 in
def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad, def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
"ldrsh", " $dst, $addr", "ldrsh", " $dst, $addr",
[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
let canFoldAsLoad = 1 in let canFoldAsLoad = 1 in
def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad, def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
"ldr", " $dst, $addr", "ldr", " $dst, $addr",
[(set tGPR:$dst, (load t_addrmode_sp:$addr))]>; [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
// Special instruction for restore. It cannot clobber condition register // Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr(). // when it's expanded by eliminateCallFramePseudoInstr().
let canFoldAsLoad = 1, mayLoad = 1 in let canFoldAsLoad = 1, mayLoad = 1 in
def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad, def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
"ldr", " $dst, $addr", []>; "ldr", " $dst, $addr", []>;
// Load tconstpool // Load tconstpool
// FIXME: Added .n suffix to workaround a Darwin assembler bug. // FIXME: Added .n suffix to workaround a Darwin assembler bug.
let canFoldAsLoad = 1 in let canFoldAsLoad = 1 in
def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad, def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
"ldr", ".n $dst, $addr", "ldr", ".n $dst, $addr",
[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools. // Special LDR for loads from non-pc-relative constpools.
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad, def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
"ldr", " $dst, $addr", []>; "ldr", " $dst, $addr", []>;
def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore, def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
"str", " $src, $addr", "str", " $src, $addr",
[(store tGPR:$src, t_addrmode_s4:$addr)]>; [(store tGPR:$src, t_addrmode_s4:$addr)]>;
def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore, def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
"strb", " $src, $addr", "strb", " $src, $addr",
[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>; [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore, def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
"strh", " $src, $addr", "strh", " $src, $addr",
[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>; [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore, def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
"str", " $src, $addr", "str", " $src, $addr",
[(store tGPR:$src, t_addrmode_sp:$addr)]>; [(store tGPR:$src, t_addrmode_sp:$addr)]>;
let mayStore = 1 in { let mayStore = 1 in {
// Special instruction for spill. It cannot clobber condition register // Special instruction for spill. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr(). // when it's expanded by eliminateCallFramePseudoInstr().
def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore, def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
"str", " $src, $addr", []>; "str", " $src, $addr", []>;
} }
@ -352,13 +352,13 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
let mayLoad = 1 in let mayLoad = 1 in
def tLDM : T1I<(outs), def tLDM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
IIC_iLoad, IIC_iLoadm,
"ldm${addr:submode}${p} $addr, $dst1", []>; "ldm${addr:submode}${p} $addr, $dst1", []>;
let mayStore = 1 in let mayStore = 1 in
def tSTM : T1I<(outs), def tSTM : T1I<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
IIC_iStore, IIC_iStorem,
"stm${addr:submode}${p} $addr, $src1", []>; "stm${addr:submode}${p} $addr, $src1", []>;
let mayLoad = 1, Uses = [SP], Defs = [SP] in let mayLoad = 1, Uses = [SP], Defs = [SP] in
@ -375,66 +375,66 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$src1, variable_ops), IIC_Br,
// Add with carry register // Add with carry register
let isCommutable = 1, Uses = [CPSR] in let isCommutable = 1, Uses = [CPSR] in
def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"adc", " $dst, $rhs", "adc", " $dst, $rhs",
[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
// Add immediate // Add immediate
def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
"add", " $dst, $lhs, $rhs", "add", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>; [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
"add", " $dst, $rhs", "add", " $dst, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>; [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
// Add register // Add register
let isCommutable = 1 in let isCommutable = 1 in
def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"add", " $dst, $lhs, $rhs", "add", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
"add", " $dst, $rhs @ addhirr", []>; "add", " $dst, $rhs @ addhirr", []>;
// And register // And register
let isCommutable = 1 in let isCommutable = 1 in
def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"and", " $dst, $rhs", "and", " $dst, $rhs",
[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
// ASR immediate // ASR immediate
def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
"asr", " $dst, $lhs, $rhs", "asr", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>; [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
// ASR register // ASR register
def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
"asr", " $dst, $rhs", "asr", " $dst, $rhs",
[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
// BIC register // BIC register
def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"bic", " $dst, $rhs", "bic", " $dst, $rhs",
[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>; [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
// CMN register // CMN register
let Defs = [CPSR] in { let Defs = [CPSR] in {
def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
"cmn", " $lhs, $rhs", "cmn", " $lhs, $rhs",
[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
"cmn", " $lhs, $rhs", "cmn", " $lhs, $rhs",
[(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>; [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
} }
// CMP immediate // CMP immediate
let Defs = [CPSR] in { let Defs = [CPSR] in {
def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
"cmp", " $lhs, $rhs", "cmp", " $lhs, $rhs",
[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>; [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
"cmp", " $lhs, $rhs", "cmp", " $lhs, $rhs",
[(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>; [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
@ -442,48 +442,48 @@ def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
// CMP register // CMP register
let Defs = [CPSR] in { let Defs = [CPSR] in {
def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
"cmp", " $lhs, $rhs", "cmp", " $lhs, $rhs",
[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>; [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
"cmp", " $lhs, $rhs", "cmp", " $lhs, $rhs",
[(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>; [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
"cmp", " $lhs, $rhs", []>; "cmp", " $lhs, $rhs", []>;
def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
"cmp", " $lhs, $rhs", []>; "cmp", " $lhs, $rhs", []>;
} }
// XOR register // XOR register
let isCommutable = 1 in let isCommutable = 1 in
def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"eor", " $dst, $rhs", "eor", " $dst, $rhs",
[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
// LSL immediate // LSL immediate
def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
"lsl", " $dst, $lhs, $rhs", "lsl", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>; [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
// LSL register // LSL register
def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
"lsl", " $dst, $rhs", "lsl", " $dst, $rhs",
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
// LSR immediate // LSR immediate
def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
"lsr", " $dst, $lhs, $rhs", "lsr", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>; [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
// LSR register // LSR register
def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
"lsr", " $dst, $rhs", "lsr", " $dst, $rhs",
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
// move register // move register
def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iALU, def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
"mov", " $dst, $src", "mov", " $dst, $src",
[(set tGPR:$dst, imm0_255:$src)]>; [(set tGPR:$dst, imm0_255:$src)]>;
@ -492,45 +492,45 @@ def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iALU,
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
// FIXME: Make this predicable. // FIXME: Make this predicable.
def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
"mov $dst, $src", []>; "mov $dst, $src", []>;
let Defs = [CPSR] in let Defs = [CPSR] in
def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
"movs $dst, $src", []>; "movs $dst, $src", []>;
// FIXME: Make these predicable. // FIXME: Make these predicable.
def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iALU, def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
"mov $dst, $src\t@ hir2lor", []>; "mov $dst, $src\t@ hir2lor", []>;
def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iALU, def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
"mov $dst, $src\t@ lor2hir", []>; "mov $dst, $src\t@ lor2hir", []>;
def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
"mov $dst, $src\t@ hir2hir", []>; "mov $dst, $src\t@ hir2hir", []>;
} // neverHasSideEffects } // neverHasSideEffects
// multiply register // multiply register
let isCommutable = 1 in let isCommutable = 1 in
def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMPYw, def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
"mul", " $dst, $rhs", "mul", " $dst, $rhs",
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
// move inverse register // move inverse register
def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
"mvn", " $dst, $src", "mvn", " $dst, $src",
[(set tGPR:$dst, (not tGPR:$src))]>; [(set tGPR:$dst, (not tGPR:$src))]>;
// bitwise or register // bitwise or register
let isCommutable = 1 in let isCommutable = 1 in
def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"orr", " $dst, $rhs", "orr", " $dst, $rhs",
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
// swaps // swaps
def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"rev", " $dst, $src", "rev", " $dst, $src",
[(set tGPR:$dst, (bswap tGPR:$src))]>, [(set tGPR:$dst, (bswap tGPR:$src))]>,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"rev16", " $dst, $src", "rev16", " $dst, $src",
[(set tGPR:$dst, [(set tGPR:$dst,
(or (and (srl tGPR:$src, (i32 8)), 0xFF), (or (and (srl tGPR:$src, (i32 8)), 0xFF),
@ -539,7 +539,7 @@ def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"revsh", " $dst, $src", "revsh", " $dst, $src",
[(set tGPR:$dst, [(set tGPR:$dst,
(sext_inreg (sext_inreg
@ -548,63 +548,63 @@ def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
// rotate right register // rotate right register
def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
"ror", " $dst, $rhs", "ror", " $dst, $rhs",
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
// negate register // negate register
def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
"rsb", " $dst, $src, #0", "rsb", " $dst, $src, #0",
[(set tGPR:$dst, (ineg tGPR:$src))]>; [(set tGPR:$dst, (ineg tGPR:$src))]>;
// Subtract with carry register // Subtract with carry register
let Uses = [CPSR] in let Uses = [CPSR] in
def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"sbc", " $dst, $rhs", "sbc", " $dst, $rhs",
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
// Subtract immediate // Subtract immediate
def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
"sub", " $dst, $lhs, $rhs", "sub", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>; [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU, def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
"sub", " $dst, $rhs", "sub", " $dst, $rhs",
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>; [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
// subtract register // subtract register
def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
"sub", " $dst, $lhs, $rhs", "sub", " $dst, $lhs, $rhs",
[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>; [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
// TODO: A7-96: STMIA - store multiple. // TODO: A7-96: STMIA - store multiple.
// sign-extend byte // sign-extend byte
def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"sxtb", " $dst, $src", "sxtb", " $dst, $src",
[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
// sign-extend short // sign-extend short
def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"sxth", " $dst, $src", "sxth", " $dst, $src",
[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
// test // test
let isCommutable = 1, Defs = [CPSR] in let isCommutable = 1, Defs = [CPSR] in
def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU, def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
"tst", " $lhs, $rhs", "tst", " $lhs, $rhs",
[(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>; [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
// zero-extend byte // zero-extend byte
def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"uxtb", " $dst, $src", "uxtb", " $dst, $src",
[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
// zero-extend short // zero-extend short
def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
"uxth", " $dst, $src", "uxth", " $dst, $src",
[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
Requires<[IsThumb1Only, HasV6]>; Requires<[IsThumb1Only, HasV6]>;
@ -620,20 +620,20 @@ let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
// 16-bit movcc in IT blocks for Thumb2. // 16-bit movcc in IT blocks for Thumb2.
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
"mov", " $dst, $rhs", []>; "mov", " $dst, $rhs", []>;
def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU, def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
"mov", " $dst, $rhs", []>; "mov", " $dst, $rhs", []>;
// tLEApcrel - Load a pc-relative address into a register without offending the // tLEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALU, def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p $dst, #$label", []>; "adr$p $dst, #$label", []>;
def tLEApcrelJT : T1I<(outs tGPR:$dst), def tLEApcrelJT : T1I<(outs tGPR:$dst),
(ins i32imm:$label, lane_cst:$id, pred:$p), (ins i32imm:$label, lane_cst:$id, pred:$p),
IIC_iALU, "adr$p $dst, #${label}_${id}", []>; IIC_iALUi, "adr$p $dst, #${label}_${id}", []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TLS Instructions // TLS Instructions

253
lib/Target/ARM/ARMInstrThumb2.td

@ -155,18 +155,18 @@ def t2addrmode_so_reg : Operand<i32>,
/// changed to modify CPSR. /// changed to modify CPSR.
multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
// shifted imm // shifted imm
def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU, def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
opc, " $dst, $src", opc, " $dst, $src",
[(set GPR:$dst, (opnode t2_so_imm:$src))]> { [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
let isAsCheapAsAMove = Cheap; let isAsCheapAsAMove = Cheap;
let isReMaterializable = ReMat; let isReMaterializable = ReMat;
} }
// register // register
def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
opc, ".w $dst, $src", opc, ".w $dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>; [(set GPR:$dst, (opnode GPR:$src))]>;
// shifted register // shifted register
def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iALU, def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
opc, ".w $dst, $src", opc, ".w $dst, $src",
[(set GPR:$dst, (opnode t2_so_reg:$src))]>; [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
} }
@ -177,17 +177,17 @@ multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
multiclass T2I_bin_irs<string opc, PatFrag opnode, multiclass T2I_bin_irs<string opc, PatFrag opnode,
bit Commutable = 0, string wide =""> { bit Commutable = 0, string wide =""> {
// shifted imm // shifted imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, " $dst, $lhs, $rhs", opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register // register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
opc, !strconcat(wide, " $dst, $lhs, $rhs"), opc, !strconcat(wide, " $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
// shifted register // shifted register
def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, !strconcat(wide, " $dst, $lhs, $rhs"), opc, !strconcat(wide, " $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
@ -202,11 +202,11 @@ multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
/// T2I_bin_irs counterpart. /// T2I_bin_irs counterpart.
multiclass T2I_rbin_is<string opc, PatFrag opnode> { multiclass T2I_rbin_is<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALU, def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
opc, ".w $dst, $rhs, $lhs", opc, ".w $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALU, def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
opc, " $dst, $rhs, $lhs", opc, " $dst, $rhs, $lhs",
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
} }
@ -216,17 +216,17 @@ multiclass T2I_rbin_is<string opc, PatFrag opnode> {
let Defs = [CPSR] in { let Defs = [CPSR] in {
multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
// shifted imm // shifted imm
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
!strconcat(opc, "s"), ".w $dst, $lhs, $rhs", !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// register // register
def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
!strconcat(opc, "s"), ".w $dst, $lhs, $rhs", !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
// shifted register // shifted register
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
!strconcat(opc, "s"), ".w $dst, $lhs, $rhs", !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
@ -236,21 +236,21 @@ multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
/// patterns for a binary operation that produces a value. /// patterns for a binary operation that produces a value.
multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
// shifted imm // shifted imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
// 12-bit imm // 12-bit imm
def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALU, def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
!strconcat(opc, "w"), " $dst, $lhs, $rhs", !strconcat(opc, "w"), " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
// register // register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
// shifted register // shifted register
def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
} }
@ -261,32 +261,32 @@ multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
let Uses = [CPSR] in { let Uses = [CPSR] in {
multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
// shifted imm // shifted imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, " $dst, $lhs, $rhs", opc, " $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUnused]>; Requires<[IsThumb2, CarryDefIsUnused]>;
// register // register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUnused]> { Requires<[IsThumb2, CarryDefIsUnused]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
// shifted register // shifted register
def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUnused]>; Requires<[IsThumb2, CarryDefIsUnused]>;
// Carry setting variants // Carry setting variants
// shifted imm // shifted imm
def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
!strconcat(opc, "s $dst, $lhs, $rhs"), !strconcat(opc, "s $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUsed]> { Requires<[IsThumb2, CarryDefIsUsed]> {
let Defs = [CPSR]; let Defs = [CPSR];
} }
// register // register
def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
!strconcat(opc, "s.w $dst, $lhs, $rhs"), !strconcat(opc, "s.w $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUsed]> { Requires<[IsThumb2, CarryDefIsUsed]> {
@ -294,7 +294,7 @@ multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
// shifted register // shifted register
def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
!strconcat(opc, "s.w $dst, $lhs, $rhs"), !strconcat(opc, "s.w $dst, $lhs, $rhs"),
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
Requires<[IsThumb2, CarryDefIsUsed]> { Requires<[IsThumb2, CarryDefIsUsed]> {
@ -308,12 +308,12 @@ let Defs = [CPSR] in {
multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
IIC_iALU, IIC_iALUi,
!strconcat(opc, "${s}.w $dst, $rhs, $lhs"), !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
// shifted register // shifted register
def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
IIC_iALU, IIC_iALUsi,
!strconcat(opc, "${s} $dst, $rhs, $lhs"), !strconcat(opc, "${s} $dst, $rhs, $lhs"),
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
} }
@ -323,30 +323,30 @@ multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
// rotate operation that produces a value. // rotate operation that produces a value.
multiclass T2I_sh_ir<string opc, PatFrag opnode> { multiclass T2I_sh_ir<string opc, PatFrag opnode> {
// 5-bit imm // 5-bit imm
def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU, def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
// register // register
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
opc, ".w $dst, $lhs, $rhs", opc, ".w $dst, $lhs, $rhs",
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
} }
/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test /// T2I_cmp_is - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
/// patterns. Similar to T2I_bin_irs except the instruction does not produce /// patterns. Similar to T2I_bin_irs except the instruction does not produce
/// a explicit result, only implicitly set CPSR. /// a explicit result, only implicitly set CPSR.
let Defs = [CPSR] in { let Defs = [CPSR] in {
multiclass T2I_cmp_is<string opc, PatFrag opnode> { multiclass T2I_cmp_is<string opc, PatFrag opnode> {
// shifted imm // shifted imm
def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU, def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi,
opc, ".w $lhs, $rhs", opc, ".w $lhs, $rhs",
[(opnode GPR:$lhs, t2_so_imm:$rhs)]>; [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
// register // register
def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU, def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
opc, ".w $lhs, $rhs", opc, ".w $lhs, $rhs",
[(opnode GPR:$lhs, GPR:$rhs)]>; [(opnode GPR:$lhs, GPR:$rhs)]>;
// shifted register // shifted register
def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU, def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi,
opc, ".w $lhs, $rhs", opc, ".w $lhs, $rhs",
[(opnode GPR:$lhs, t2_so_reg:$rhs)]>; [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
} }
@ -354,42 +354,42 @@ multiclass T2I_cmp_is<string opc, PatFrag opnode> {
/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
multiclass T2I_ld<string opc, PatFrag opnode> { multiclass T2I_ld<string opc, PatFrag opnode> {
def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoad, def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi,
opc, ".w $dst, $addr", opc, ".w $dst, $addr",
[(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoad, def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi,
opc, " $dst, $addr", opc, " $dst, $addr",
[(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoad, def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr,
opc, ".w $dst, $addr", opc, ".w $dst, $addr",
[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad, def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
opc, ".w $dst, $addr", opc, ".w $dst, $addr",
[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>; [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
} }
/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
multiclass T2I_st<string opc, PatFrag opnode> { multiclass T2I_st<string opc, PatFrag opnode> {
def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStore, def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei,
opc, ".w $src, $addr", opc, ".w $src, $addr",
[(opnode GPR:$src, t2addrmode_imm12:$addr)]>; [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStore, def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei,
opc, " $src, $addr", opc, " $src, $addr",
[(opnode GPR:$src, t2addrmode_imm8:$addr)]>; [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStore, def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer,
opc, ".w $src, $addr", opc, ".w $src, $addr",
[(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
} }
/// T2I_picld - Defines the PIC load pattern. /// T2I_picld - Defines the PIC load pattern.
class T2I_picld<string opc, PatFrag opnode> : class T2I_picld<string opc, PatFrag opnode> :
T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoad, T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi,
!strconcat("${addr:label}:\n\t", opc), " $dst, $addr", !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
[(set GPR:$dst, (opnode addrmodepc:$addr))]>; [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
/// T2I_picst - Defines the PIC store pattern. /// T2I_picst - Defines the PIC store pattern.
class T2I_picst<string opc, PatFrag opnode> : class T2I_picst<string opc, PatFrag opnode> :
T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStore, T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer,
!strconcat("${addr:label}:\n\t", opc), " $src, $addr", !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
[(opnode GPR:$src, addrmodepc:$addr)]>; [(opnode GPR:$src, addrmodepc:$addr)]>;
@ -397,22 +397,22 @@ class T2I_picst<string opc, PatFrag opnode> :
/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_unary_rrot<string opc, PatFrag opnode> { multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
def r : T2I<(outs GPR:$dst), (ins GPR:$Src), IIC_iALU, def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
opc, ".w $dst, $Src", opc, ".w $dst, $src",
[(set GPR:$dst, (opnode GPR:$Src))]>; [(set GPR:$dst, (opnode GPR:$src))]>;
def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), IIC_iALU, def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
opc, ".w $dst, $Src, ror $rot", opc, ".w $dst, $src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>; [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>;
} }
/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_bin_rrot<string opc, PatFrag opnode> { multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALU, def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
opc, " $dst, $LHS, $RHS", opc, " $dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
IIC_iALU, opc, " $dst, $LHS, $RHS, ror $rot", IIC_iALUsr, opc, " $dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS, [(set GPR:$dst, (opnode GPR:$LHS,
(rotr GPR:$RHS, rot_imm:$rot)))]>; (rotr GPR:$RHS, rot_imm:$rot)))]>;
} }
@ -427,31 +427,32 @@ multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
// LEApcrel - Load a pc-relative address into a register without offending the // LEApcrel - Load a pc-relative address into a register without offending the
// assembler. // assembler.
def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALU, def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p.w $dst, #$label", []>; "adr$p.w $dst, #$label", []>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst), def t2LEApcrelJT : T2XI<(outs GPR:$dst),
(ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALU, (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALUi,
"adr$p.w $dst, #${label}_${id}", []>; "adr$p.w $dst, #${label}_${id}", []>;
// ADD r, sp, {so_imm|i12} // ADD r, sp, {so_imm|i12}
def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU, def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
"add", ".w $dst, $sp, $imm", []>; IIC_iALUi, "add", ".w $dst, $sp, $imm", []>;
def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), IIC_iALU, def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
"addw", " $dst, $sp, $imm", []>; IIC_iALUi, "addw", " $dst, $sp, $imm", []>;
// ADD r, sp, so_reg // ADD r, sp, so_reg
def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), IIC_iALU, def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
"add", ".w $dst, $sp, $rhs", []>; IIC_iALUsi, "add", ".w $dst, $sp, $rhs", []>;
// SUB r, sp, {so_imm|i12} // SUB r, sp, {so_imm|i12}
def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU, def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
"sub", ".w $dst, $sp, $imm", []>; IIC_iALUi, "sub", ".w $dst, $sp, $imm", []>;
def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), IIC_iALU, def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
"subw", " $dst, $sp, $imm", []>; IIC_iALUi, "subw", " $dst, $sp, $imm", []>;
// SUB r, sp, so_reg // SUB r, sp, so_reg
def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), IIC_iALU, def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
IIC_iALUsi,
"sub", " $dst, $sp, $rhs", []>; "sub", " $dst, $sp, $rhs", []>;
@ -485,8 +486,8 @@ defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
let mayLoad = 1 in { let mayLoad = 1 in {
// Load doubleword // Load doubleword
def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr), def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
IIC_iLoad, "ldrd", " $dst, $addr", []>; IIC_iLoadi, "ldrd", " $dst, $addr", []>;
def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad, def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
"ldrd", " $dst, $addr", []>; "ldrd", " $dst, $addr", []>;
} }
@ -534,57 +535,57 @@ def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
let mayLoad = 1 in { let mayLoad = 1 in {
def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr), (ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad, AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
"ldr", " $dst, $addr!", "$addr.base = $base_wb", "ldr", " $dst, $addr!", "$addr.base = $base_wb",
[]>; []>;
def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad, AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
"ldr", " $dst, [$base], $offset", "$base = $base_wb", "ldr", " $dst, [$base], $offset", "$base = $base_wb",
[]>; []>;
def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr), (ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad, AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
"ldrb", " $dst, $addr!", "$addr.base = $base_wb", "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
[]>; []>;
def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad, AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
"ldrb", " $dst, [$base], $offset", "$base = $base_wb", "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
[]>; []>;
def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr), (ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad, AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
"ldrh", " $dst, $addr!", "$addr.base = $base_wb", "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
[]>; []>;
def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad, AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
"ldrh", " $dst, [$base], $offset", "$base = $base_wb", "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
[]>; []>;
def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr), (ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad, AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
"ldrsb", " $dst, $addr!", "$addr.base = $base_wb", "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
[]>; []>;
def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad, AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
"ldrsb", " $dst, [$base], $offset", "$base = $base_wb", "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
[]>; []>;
def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr), (ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad, AddrModeT2_i8, IndexModePre, IIC_iLoadiu,
"ldrsh", " $dst, $addr!", "$addr.base = $base_wb", "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
[]>; []>;
def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iLoad, AddrModeT2_i8, IndexModePost, IIC_iLoadiu,
"ldrsh", " $dst, [$base], $offset", "$base = $base_wb", "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
[]>; []>;
} }
@ -597,47 +598,47 @@ defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
// Store doubleword // Store doubleword
let mayLoad = 1 in let mayLoad = 1 in
def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
IIC_iStore, "strd", " $src, $addr", []>; IIC_iStorer, "strd", " $src, $addr", []>;
// Indexed stores // Indexed stores
def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePre, IIC_iStore, AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
"str", " $src, [$base, $offset]!", "$base = $base_wb", "str", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStore, AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
"str", " $src, [$base], $offset", "$base = $base_wb", "str", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePre, IIC_iStore, AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
"strh", " $src, [$base, $offset]!", "$base = $base_wb", "strh", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStore, AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
"strh", " $src, [$base], $offset", "$base = $base_wb", "strh", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePre, IIC_iStore, AddrModeT2_i8, IndexModePre, IIC_iStoreiu,
"strb", " $src, [$base, $offset]!", "$base = $base_wb", "strb", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost, IIC_iStore, AddrModeT2_i8, IndexModePost, IIC_iStoreiu,
"strb", " $src, [$base], $offset", "$base = $base_wb", "strb", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
@ -652,34 +653,34 @@ def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
let mayLoad = 1 in let mayLoad = 1 in
def t2LDM : T2XI<(outs), def t2LDM : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
IIC_iLoad, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1", []>; IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1", []>;
let mayStore = 1 in let mayStore = 1 in
def t2STM : T2XI<(outs), def t2STM : T2XI<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
IIC_iStore, "stm${addr:submode}${p}${addr:wide} $addr, $src1", []>; IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $src1", []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Move Instructions. // Move Instructions.
// //
let neverHasSideEffects = 1 in let neverHasSideEffects = 1 in
def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
"mov", ".w $dst, $src", []>; "mov", ".w $dst, $src", []>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU, def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
"mov", ".w $dst, $src", "mov", ".w $dst, $src",
[(set GPR:$dst, t2_so_imm:$src)]>; [(set GPR:$dst, t2_so_imm:$src)]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iALU, def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
"movw", " $dst, $src", "movw", " $dst, $src",
[(set GPR:$dst, imm0_65535:$src)]>; [(set GPR:$dst, imm0_65535:$src)]>;
// FIXME: Also available in ARM mode. // FIXME: Also available in ARM mode.
let Constraints = "$src = $dst" in let Constraints = "$src = $dst" in
def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iALU, def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
"movt", " $dst, $imm", "movt", " $dst, $imm",
[(set GPR:$dst, [(set GPR:$dst,
(or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
@ -755,15 +756,15 @@ defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
"rrx", ".w $dst, $src", "rrx", ".w $dst, $src",
[(set GPR:$dst, (ARMrrx GPR:$src))]>; [(set GPR:$dst, (ARMrrx GPR:$src))]>;
let Defs = [CPSR] in { let Defs = [CPSR] in {
def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
"lsrs.w $dst, $src, #1", "lsrs.w $dst, $src, #1",
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
"asrs.w $dst, $src, #1", "asrs.w $dst, $src, #1",
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>; [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
} }
@ -779,8 +780,8 @@ defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
let Constraints = "$src = $dst" in let Constraints = "$src = $dst" in
def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), IIC_iALU, def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
"bfc", " $dst, $imm", IIC_iALUi, "bfc", " $dst, $imm",
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
@ -807,80 +808,80 @@ def : T2Pat<(t2_so_imm_not:$src),
// Multiply Instructions. // Multiply Instructions.
// //
let isCommutable = 1 in let isCommutable = 1 in
def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
"mul", " $dst, $a, $b", "mul", " $dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw, def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
"mla", " $dst, $a, $b, $c", "mla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw, def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
"mls", " $dst, $a, $b, $c", "mls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
// Extra precision multiplies with low / high results // Extra precision multiplies with low / high results
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
let isCommutable = 1 in { let isCommutable = 1 in {
def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl, def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
"smull", " $ldst, $hdst, $a, $b", []>; "smull", " $ldst, $hdst, $a, $b", []>;
def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl, def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
"umull", " $ldst, $hdst, $a, $b", []>; "umull", " $ldst, $hdst, $a, $b", []>;
} }
// Multiply + accumulate // Multiply + accumulate
def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl, def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
"smlal", " $ldst, $hdst, $a, $b", []>; "smlal", " $ldst, $hdst, $a, $b", []>;
def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl, def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
"umlal", " $ldst, $hdst, $a, $b", []>; "umlal", " $ldst, $hdst, $a, $b", []>;
def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl, def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
"umaal", " $ldst, $hdst, $a, $b", []>; "umaal", " $ldst, $hdst, $a, $b", []>;
} // neverHasSideEffects } // neverHasSideEffects
// Most significant word multiply // Most significant word multiply
def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
"smmul", " $dst, $a, $b", "smmul", " $dst, $a, $b",
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw, def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
"smmla", " $dst, $a, $b, $c", "smmla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw, def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
"smmls", " $dst, $a, $b, $c", "smmls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
multiclass T2I_smul<string opc, PatFrag opnode> { multiclass T2I_smul<string opc, PatFrag opnode> {
def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
!strconcat(opc, "bb"), " $dst, $a, $b", !strconcat(opc, "bb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16)))]>; (sext_inreg GPR:$b, i16)))]>;
def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
!strconcat(opc, "bt"), " $dst, $a, $b", !strconcat(opc, "bt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, (i32 16))))]>; (sra GPR:$b, (i32 16))))]>;
def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
!strconcat(opc, "tb"), " $dst, $a, $b", !strconcat(opc, "tb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
(sext_inreg GPR:$b, i16)))]>; (sext_inreg GPR:$b, i16)))]>;
def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw, def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
!strconcat(opc, "tt"), " $dst, $a, $b", !strconcat(opc, "tt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
(sra GPR:$b, (i32 16))))]>; (sra GPR:$b, (i32 16))))]>;
def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYh, def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
!strconcat(opc, "wb"), " $dst, $a, $b", !strconcat(opc, "wb"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a, [(set GPR:$dst, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), (i32 16)))]>; (sext_inreg GPR:$b, i16)), (i32 16)))]>;
def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYh, def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
!strconcat(opc, "wt"), " $dst, $a, $b", !strconcat(opc, "wt"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a, [(set GPR:$dst, (sra (opnode GPR:$a,
(sra GPR:$b, (i32 16))), (i32 16)))]>; (sra GPR:$b, (i32 16))), (i32 16)))]>;
@ -888,33 +889,33 @@ multiclass T2I_smul<string opc, PatFrag opnode> {
multiclass T2I_smla<string opc, PatFrag opnode> { multiclass T2I_smla<string opc, PatFrag opnode> {
def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw, def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
!strconcat(opc, "bb"), " $dst, $a, $b, $acc", !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, [(set GPR:$dst, (add GPR:$acc,
(opnode (sext_inreg GPR:$a, i16), (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16))))]>; (sext_inreg GPR:$b, i16))))]>;
def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw, def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
!strconcat(opc, "bt"), " $dst, $a, $b, $acc", !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, (i32 16)))))]>; (sra GPR:$b, (i32 16)))))]>;
def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw, def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
!strconcat(opc, "tb"), " $dst, $a, $b, $acc", !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
(sext_inreg GPR:$b, i16))))]>; (sext_inreg GPR:$b, i16))))]>;
def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw, def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
!strconcat(opc, "tt"), " $dst, $a, $b, $acc", !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
(sra GPR:$b, (i32 16)))))]>; (sra GPR:$b, (i32 16)))))]>;
def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw, def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
!strconcat(opc, "wb"), " $dst, $a, $b, $acc", !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), (i32 16))))]>; (sext_inreg GPR:$b, i16)), (i32 16))))]>;
def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw, def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
!strconcat(opc, "wt"), " $dst, $a, $b, $acc", !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sra GPR:$b, (i32 16))), (i32 16))))]>; (sra GPR:$b, (i32 16))), (i32 16))))]>;
@ -931,15 +932,15 @@ defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
// Misc. Arithmetic Instructions. // Misc. Arithmetic Instructions.
// //
def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"clz", " $dst, $src", "clz", " $dst, $src",
[(set GPR:$dst, (ctlz GPR:$src))]>; [(set GPR:$dst, (ctlz GPR:$src))]>;
def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"rev", ".w $dst, $src", "rev", ".w $dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>; [(set GPR:$dst, (bswap GPR:$src))]>;
def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"rev16", ".w $dst, $src", "rev16", ".w $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(or (and (srl GPR:$src, (i32 8)), 0xFF), (or (and (srl GPR:$src, (i32 8)), 0xFF),
@ -947,7 +948,7 @@ def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
(or (and (srl GPR:$src, (i32 8)), 0xFF0000), (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU, def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
"revsh", ".w $dst, $src", "revsh", ".w $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(sext_inreg (sext_inreg
@ -955,7 +956,7 @@ def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
(shl GPR:$src, (i32 8))), i16))]>; (shl GPR:$src, (i32 8))), i16))]>;
def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
IIC_iALU, "pkhbt", " $dst, $src1, $src2, LSL $shamt", IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
(and (shl GPR:$src2, (i32 imm:$shamt)), (and (shl GPR:$src2, (i32 imm:$shamt)),
0xFFFF0000)))]>; 0xFFFF0000)))]>;
@ -967,7 +968,7 @@ def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
(t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
IIC_iALU, "pkhtb", " $dst, $src1, $src2, ASR $shamt", IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
(and (sra GPR:$src2, imm16_31:$shamt), (and (sra GPR:$src2, imm16_31:$shamt),
0xFFFF)))]>; 0xFFFF)))]>;
@ -1013,27 +1014,27 @@ defm t2TEQ : T2I_cmp_is<"teq",
// Conditional moves // Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iALU, def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
"mov", ".w $dst, $true", "mov", ".w $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), IIC_iALU, def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
"mov", ".w $dst, $true", IIC_iCMOVi, "mov", ".w $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
IIC_iALU, "lsl", ".w $dst, $true, $rhs", []>, IIC_iCMOVsi, "lsl", ".w $dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
IIC_iALU, "lsr", ".w $dst, $true, $rhs", []>, IIC_iCMOVsi, "lsr", ".w $dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
IIC_iALU, "asr", ".w $dst, $true, $rhs", []>, IIC_iCMOVsi, "asr", ".w $dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
IIC_iALU, "ror", ".w $dst, $true, $rhs", []>, IIC_iCMOVsi, "ror", ".w $dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -1131,7 +1132,7 @@ def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
// IT block // IT block
def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
AddrModeNone, Size2Bytes, IIC_iALU, AddrModeNone, Size2Bytes, IIC_iALUx,
"it$mask $cc", "", []>; "it$mask $cc", "", []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

108
lib/Target/ARM/ARMSchedule.td

@ -19,29 +19,103 @@ def FU_LdSt1 : FuncUnit; // pipeline 1 load/store
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM // Instruction Itinerary classes used for ARM
// //
def IIC_iALU : InstrItinClass; def IIC_iALUx : InstrItinClass;
def IIC_iMPYh : InstrItinClass; def IIC_iALUi : InstrItinClass;
def IIC_iMPYw : InstrItinClass; def IIC_iALUr : InstrItinClass;
def IIC_iMPYl : InstrItinClass; def IIC_iALUsi : InstrItinClass;
def IIC_iLoad : InstrItinClass; def IIC_iALUsr : InstrItinClass;
def IIC_iStore : InstrItinClass; def IIC_iUNAr : InstrItinClass;
def IIC_fpALU : InstrItinClass; def IIC_iUNAsi : InstrItinClass;
def IIC_fpMPY : InstrItinClass; def IIC_iUNAsr : InstrItinClass;
def IIC_fpLoad : InstrItinClass; def IIC_iCMPi : InstrItinClass;
def IIC_fpStore : InstrItinClass; def IIC_iCMPr : InstrItinClass;
def IIC_Br : InstrItinClass; def IIC_iCMPsi : InstrItinClass;
def IIC_iCMPsr : InstrItinClass;
def IIC_iMOVi : InstrItinClass;
def IIC_iMOVr : InstrItinClass;
def IIC_iMOVsi : InstrItinClass;
def IIC_iMOVsr : InstrItinClass;
def IIC_iCMOVi : InstrItinClass;
def IIC_iCMOVr : InstrItinClass;
def IIC_iCMOVsi : InstrItinClass;
def IIC_iCMOVsr : InstrItinClass;
def IIC_iMUL16 : InstrItinClass;
def IIC_iMAC16 : InstrItinClass;
def IIC_iMUL32 : InstrItinClass;
def IIC_iMAC32 : InstrItinClass;
def IIC_iMUL64 : InstrItinClass;
def IIC_iMAC64 : InstrItinClass;
def IIC_iLoadi : InstrItinClass;
def IIC_iLoadr : InstrItinClass;
def IIC_iLoadsi : InstrItinClass;
def IIC_iLoadiu : InstrItinClass;
def IIC_iLoadru : InstrItinClass;
def IIC_iLoadsiu : InstrItinClass;
def IIC_iLoadm : InstrItinClass;
def IIC_iStorei : InstrItinClass;
def IIC_iStorer : InstrItinClass;
def IIC_iStoresi : InstrItinClass;
def IIC_iStoreiu : InstrItinClass;
def IIC_iStoreru : InstrItinClass;
def IIC_iStoresiu : InstrItinClass;
def IIC_iStorem : InstrItinClass;
def IIC_fpALU : InstrItinClass;
def IIC_fpMPY : InstrItinClass;
def IIC_fpLoad : InstrItinClass;
def IIC_fpStore : InstrItinClass;
def IIC_Br : InstrItinClass;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Processor instruction itineraries. // Processor instruction itineraries.
def GenericItineraries : ProcessorItineraries<[ def GenericItineraries : ProcessorItineraries<[
InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYh , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYw , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYl , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>, InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
InstrStage<2, [FU_LdSt0]>]>,
InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,

52
lib/Target/ARM/ARMScheduleV6.td

@ -14,13 +14,53 @@
// TODO: this should model an ARM11 // TODO: this should model an ARM11
// Single issue pipeline so every itinerary starts with FU_pipe0 // Single issue pipeline so every itinerary starts with FU_pipe0
def V6Itineraries : ProcessorItineraries<[ def V6Itineraries : ProcessorItineraries<[
InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYh , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYw , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYl , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>, InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
InstrStage<2, [FU_LdSt0]>]>,
InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,

209
lib/Target/ARM/ARMScheduleV7.td

@ -11,25 +11,154 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//
// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
//
// Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1 // Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
//
def CortexA8Itineraries : ProcessorItineraries<[ def CortexA8Itineraries : ProcessorItineraries<[
// two fully-pipelined integer ALU pipelines
InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>, // Two fully-pipelined integer ALU pipelines
// integer Multiply pipeline //
InstrItinData<IIC_iMPYh , [InstrStage<1, [FU_Pipe0]>]>, // No operand cycles
InstrItinData<IIC_iMPYw , [InstrStage<1, [FU_Pipe1], 0>, InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
InstrStage<2, [FU_Pipe0]>]>, //
InstrItinData<IIC_iMPYl , [InstrStage<2, [FU_Pipe1], 0>, // Binary Instructions that produce a result
InstrStage<3, [FU_Pipe0]>]>, InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
//
// Unary Instructions that produce a result
InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
//
// Compare instructions
InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
//
// Move instructions, unconditional
InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
//
// Move instructions, conditional
InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
// Integer multiply pipeline
// Result written in E5, but that is relative to the last cycle of multicycle,
// so we use 6 for those cases
//
InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
// Integer load pipeline
//
// loads have an extra cycle of latency, but are fully pipelined // loads have an extra cycle of latency, but are fully pipelined
// use FU_Issue to enforce the 1 load/store per cycle limit // use FU_Issue to enforce the 1 load/store per cycle limit
InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Issue], 0>, //
InstrStage<1, [FU_Pipe0, FU_Pipe1]>, // Immediate offset
InstrStage<1, [FU_LdSt0]>]>, InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
// fully-pipelined stores InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 1]>,
//
// Register offset
InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
//
// Scaled register offset, issues over 2 cycles
InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
InstrStage<1, [FU_Pipe1], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
//
// Immediate offset with update
InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
//
// Register offset with update
InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
//
// Scaled register offset with update, issues over 2 cycles
InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
InstrStage<1, [FU_Pipe1], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
//
// Load multiple
InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
InstrStage<2, [FU_Pipe0], 0>,
InstrStage<2, [FU_Pipe1], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>]>,
// Integer store pipeline
//
// use FU_Issue to enforce the 1 load/store per cycle limit // use FU_Issue to enforce the 1 load/store per cycle limit
InstrItinData<IIC_iStore , [InstrStage<1, [FU_Issue], 0>, //
InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>, // Immediate offset
InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1]>,
//
// Register offset
InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1, 1]>,
//
// Scaled register offset, issues over 2 cycles
InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
InstrStage<1, [FU_Pipe1], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
//
// Immediate offset with update
InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
//
// Register offset with update
InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
//
// Scaled register offset with update, issues over 2 cycles
InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
InstrStage<1, [FU_Pipe0], 0>,
InstrStage<1, [FU_Pipe1], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
//
// Store multiple
InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
InstrStage<2, [FU_Pipe0], 0>,
InstrStage<2, [FU_Pipe1], 0>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_LdSt0]>]>,
// Branch
//
// no delay slots, so the latency of a branch is unimportant // no delay slots, so the latency of a branch is unimportant
InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>, InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
@ -51,13 +180,53 @@ def CortexA8Itineraries : ProcessorItineraries<[
// FIXME // FIXME
def CortexA9Itineraries : ProcessorItineraries<[ def CortexA9Itineraries : ProcessorItineraries<[
InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYh , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYw , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMPYl , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>, InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
InstrStage<1, [FU_LdSt0]>]>,
InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
InstrStage<2, [FU_LdSt0]>]>,
InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,