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ARM LDM encoding for the mode (ia, ib, da, db) operand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-10 23:38:36 +00:00
parent c87a94a942
commit 5d5eb9e381
4 changed files with 19 additions and 1 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -177,6 +177,8 @@ namespace {
const { return 0; }
unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
const {return 0; }
uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
const { return 0; }

4
lib/Target/ARM/ARMInstrFormats.td
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@ -942,8 +942,10 @@ class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
asm, cstr, pattern> {
bits<16> dsts;
bits<4> Rn;
bits<2> amode;
let Inst{27-25} = 0b100;
let Inst{24-22} = 0b010;
let Inst{24-23} = amode;
let Inst{22} = 0; // S bit
let Inst{20} = 1; // L bit
let Inst{19-16} = Rn;
let Inst{15-0} = dsts;

1
lib/Target/ARM/ARMInstrInfo.td
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@ -456,6 +456,7 @@ def am3offset : Operand<i32>,
// ldstm_mode := {ia, ib, da, db}
//
def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
string EncoderMethod = "getLdStmModeOpValue";
let PrintMethod = "printLdStmModeOperand";
}

13
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -82,6 +82,19 @@ public:
uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getLdStmModeOpValue - Return encoding for load/store multiple mode.
uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
switch (Mode) {
default: assert(0 && "Unknown addressing sub-mode!");
case ARM_AM::da: return 0;
case ARM_AM::ia: return 1;
case ARM_AM::db: return 2;
case ARM_AM::ib: return 3;
}
}
/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;