mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
[FastISel][AArch64] Use the correct register class to make the MI verifier happy.
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
95ca0fb247
commit
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@ -247,7 +247,7 @@ unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
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unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addFrameIndex(SI->second)
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@ -271,9 +271,8 @@ unsigned AArch64FastISel::AArch64MaterializeInt(const ConstantInt *CI, MVT VT) {
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: &AArch64::GPR32RegClass;
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unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(ZeroReg, getKillRegState(true));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(ZeroReg, getKillRegState(true));
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return ResultReg;
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}
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@ -686,7 +685,7 @@ bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
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// the alloca address into a register, set the base type back to register and
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// continue. This should almost never happen.
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if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
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unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
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unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addFrameIndex(Addr.getFI())
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@ -698,14 +697,12 @@ bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
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if (RegisterOffsetNeedsLowering) {
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unsigned ResultReg = 0;
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if (Addr.getReg()) {
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ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::ADDXrs), ResultReg)
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.addReg(Addr.getReg())
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.addReg(Addr.getOffsetReg())
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.addImm(Addr.getShift());
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} else
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if (Addr.getReg())
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ResultReg = FastEmitInst_rri(AArch64::ADDXrs, &AArch64::GPR64RegClass,
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Addr.getReg(), /*TODO:IsKill=*/false,
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Addr.getOffsetReg(), /*TODO:IsKill=*/false,
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Addr.getShift());
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else
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ResultReg = Emit_LSL_ri(MVT::i64, Addr.getOffsetReg(),
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/*Op0IsKill=*/false, Addr.getShift());
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if (!ResultReg)
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@ -752,6 +749,12 @@ void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
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MIB.addFrameIndex(FI).addImm(Offset);
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} else {
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assert(Addr.isRegBase() && "Unexpected address kind.");
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const MCInstrDesc &II = MIB->getDesc();
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unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
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Addr.setReg(
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constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
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Addr.setOffsetReg(
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constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
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if (Addr.getOffsetReg()) {
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assert(Addr.getOffset() == 0 && "Unexpected offset");
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bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
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@ -900,12 +903,17 @@ unsigned AArch64FastISel::emitAddsSubs_rr(bool UseAdds, MVT RetVT,
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};
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unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
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unsigned ResultReg;
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if (WantResult)
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ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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else
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if (WantResult) {
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const TargetRegisterClass *RC =
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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ResultReg = createResultReg(RC);
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} else
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ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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const MCInstrDesc &II = TII.get(Opc);
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LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
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RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill))
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.addReg(RHSReg, getKillRegState(RHSIsKill));
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@ -935,12 +943,16 @@ unsigned AArch64FastISel::emitAddsSubs_ri(bool UseAdds, MVT RetVT,
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};
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unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
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unsigned ResultReg;
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if (WantResult)
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ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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else
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if (WantResult) {
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const TargetRegisterClass *RC =
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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ResultReg = createResultReg(RC);
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} else
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ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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const MCInstrDesc &II = TII.get(Opc);
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LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill))
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.addImm(Imm)
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.addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
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@ -964,12 +976,17 @@ unsigned AArch64FastISel::emitAddsSubs_rs(bool UseAdds, MVT RetVT,
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};
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unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
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unsigned ResultReg;
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if (WantResult)
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ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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else
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if (WantResult) {
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const TargetRegisterClass *RC =
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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ResultReg = createResultReg(RC);
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} else
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ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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const MCInstrDesc &II = TII.get(Opc);
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LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
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RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill))
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.addReg(RHSReg, getKillRegState(RHSIsKill))
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.addImm(getShifterImm(ShiftType, ShiftImm));
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@ -993,12 +1010,17 @@ unsigned AArch64FastISel::emitAddsSubs_rx(bool UseAdds, MVT RetVT,
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};
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unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
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unsigned ResultReg;
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if (WantResult)
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ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
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else
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if (WantResult) {
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const TargetRegisterClass *RC =
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(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
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ResultReg = createResultReg(RC);
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} else
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ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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const MCInstrDesc &II = TII.get(Opc);
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LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
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RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
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.addReg(LHSReg, getKillRegState(LHSIsKill))
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.addReg(RHSReg, getKillRegState(RHSIsKill))
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.addImm(getArithExtendImm(ExtType, ShiftImm));
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@ -1290,9 +1312,10 @@ bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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SrcReg = ANDReg;
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}
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// Create the base instruction, then add the operands.
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MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(Opc))
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.addReg(SrcReg);
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const MCInstrDesc &II = TII.get(Opc);
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SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
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MachineInstrBuilder MIB =
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
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AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
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return true;
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@ -1517,8 +1540,9 @@ bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
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return false;
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// Emit the indirect branch.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
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.addReg(AddrReg);
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const MCInstrDesc &II = TII.get(AArch64::BR);
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AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
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// Make sure the CFG is up-to-date.
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for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
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@ -1565,12 +1589,17 @@ bool AArch64FastISel::SelectSelect(const Instruction *I) {
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return false;
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unsigned SelectOpc;
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const TargetRegisterClass *RC = nullptr;
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switch (DestVT.SimpleTy) {
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default: return false;
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case MVT::i32: SelectOpc = AArch64::CSELWr; break;
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case MVT::i64: SelectOpc = AArch64::CSELXr; break;
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case MVT::f32: SelectOpc = AArch64::FCSELSrrr; break;
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case MVT::f64: SelectOpc = AArch64::FCSELDrrr; break;
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case MVT::i32:
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SelectOpc = AArch64::CSELWr; RC = &AArch64::GPR32RegClass; break;
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case MVT::i64:
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SelectOpc = AArch64::CSELXr; RC = &AArch64::GPR64RegClass; break;
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case MVT::f32:
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SelectOpc = AArch64::FCSELSrrr; RC = &AArch64::FPR32RegClass; break;
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case MVT::f64:
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SelectOpc = AArch64::FCSELDrrr; RC = &AArch64::FPR64RegClass; break;
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}
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const Value *Cond = SI->getCondition();
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@ -1599,13 +1628,8 @@ bool AArch64FastISel::SelectSelect(const Instruction *I) {
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if (!TrueReg || !FalseReg)
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return false;
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
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ResultReg)
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.addReg(TrueReg, getKillRegState(TrueIsKill))
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.addReg(FalseReg, getKillRegState(FalseIsKill))
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.addImm(CC);
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unsigned ResultReg = FastEmitInst_rri(SelectOpc, RC, TrueReg, TrueIsKill,
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FalseReg, FalseIsKill, CC);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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@ -1684,8 +1708,9 @@ bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
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"Unexpected value type.");
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unsigned SrcReg = getRegForValue(I->getOperand(0));
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if (SrcReg == 0)
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if (!SrcReg)
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return false;
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bool SrcIsKill = hasTrivialKill(I->getOperand(0));
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EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
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@ -1693,13 +1718,11 @@ bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
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if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
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SrcReg =
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EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
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if (SrcReg == 0)
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if (!SrcReg)
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return false;
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SrcIsKill = true;
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}
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MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
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: &AArch64::GPR32RegClass);
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unsigned Opc;
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if (SrcVT == MVT::i64) {
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if (Signed)
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@ -1713,9 +1736,8 @@ bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
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Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
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}
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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.addReg(SrcReg);
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unsigned ResultReg = FastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
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SrcIsKill);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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@ -1790,16 +1812,22 @@ bool AArch64FastISel::FastLowerArguments() {
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for (auto const &Arg : F->args()) {
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MVT VT = TLI.getSimpleValueType(Arg.getType());
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unsigned SrcReg;
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const TargetRegisterClass *RC = nullptr;
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switch (VT.SimpleTy) {
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default: llvm_unreachable("Unexpected value type.");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16: VT = MVT::i32; // fall-through
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case MVT::i32: SrcReg = Registers[0][GPRIdx++]; break;
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case MVT::i64: SrcReg = Registers[1][GPRIdx++]; break;
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case MVT::f16: SrcReg = Registers[2][FPRIdx++]; break;
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case MVT::f32: SrcReg = Registers[3][FPRIdx++]; break;
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case MVT::f64: SrcReg = Registers[4][FPRIdx++]; break;
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case MVT::i32:
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SrcReg = Registers[0][GPRIdx++]; RC = &AArch64::GPR32RegClass; break;
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case MVT::i64:
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SrcReg = Registers[1][GPRIdx++]; RC = &AArch64::GPR64RegClass; break;
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case MVT::f16:
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SrcReg = Registers[2][FPRIdx++]; RC = &AArch64::FPR16RegClass; break;
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case MVT::f32:
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SrcReg = Registers[3][FPRIdx++]; RC = &AArch64::FPR32RegClass; break;
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case MVT::f64:
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SrcReg = Registers[4][FPRIdx++]; RC = &AArch64::FPR64RegClass; break;
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}
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// Skip unused arguments.
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@ -1808,7 +1836,6 @@ bool AArch64FastISel::FastLowerArguments() {
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continue;
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}
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const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
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unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
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// FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
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// Without this, EmitLiveInCopies may eliminate the livein if its only
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@ -1816,7 +1843,7 @@ bool AArch64FastISel::FastLowerArguments() {
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(DstReg, getKillRegState(true));
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.addReg(DstReg, getKillRegState(true));
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UpdateValueMap(&Arg, ResultReg);
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}
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return true;
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@ -1937,7 +1964,7 @@ bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(RVLocs[0].getLocReg());
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.addReg(RVLocs[0].getLocReg());
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CLI.InRegs.push_back(RVLocs[0].getLocReg());
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CLI.ResultReg = ResultReg;
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@ -2192,8 +2219,9 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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static_cast<const AArch64RegisterInfo *>(
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TM.getSubtargetImpl()->getRegisterInfo());
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unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
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unsigned SrcReg = FramePtr;
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unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
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// Recursively load frame address
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// ldr x0, [fp]
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// ldr x0, [x0]
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@ -2202,10 +2230,9 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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unsigned DestReg;
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unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
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while (Depth--) {
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DestReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::LDRXui), DestReg)
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.addReg(SrcReg).addImm(0);
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DestReg = FastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
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SrcReg, /*IsKill=*/true, 0);
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assert(DestReg && "Unexpected LDR instruction emission failure.");
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SrcReg = DestReg;
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}
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@ -2298,7 +2325,6 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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const Function *Callee = II->getCalledFunction();
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auto *Ty = cast<StructType>(Callee->getReturnType());
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Type *RetTy = Ty->getTypeAtIndex(0U);
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Type *CondTy = Ty->getTypeAtIndex(1);
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MVT VT;
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if (!isTypeLegal(RetTy, VT))
|
||||
@ -2394,15 +2420,11 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
|
||||
}
|
||||
|
||||
ResultReg2 = FuncInfo.CreateRegs(CondTy);
|
||||
ResultReg2 = FastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
|
||||
AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
|
||||
/*IsKill=*/true, getInvertedCondCode(CC));
|
||||
assert((ResultReg1 + 1) == ResultReg2 &&
|
||||
"Nonconsecutive result registers.");
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
|
||||
ResultReg2)
|
||||
.addReg(AArch64::WZR, getKillRegState(true))
|
||||
.addReg(AArch64::WZR, getKillRegState(true))
|
||||
.addImm(getInvertedCondCode(CC));
|
||||
|
||||
UpdateValueMap(II, ResultReg1, 2);
|
||||
return true;
|
||||
}
|
||||
@ -2586,13 +2608,8 @@ unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
|
||||
// FIXME: We're SExt i1 to i64.
|
||||
return 0;
|
||||
}
|
||||
unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
|
||||
ResultReg)
|
||||
.addReg(SrcReg)
|
||||
.addImm(0)
|
||||
.addImm(0);
|
||||
return ResultReg;
|
||||
return FastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
|
||||
/*TODO:IsKill=*/false, 0, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2610,14 +2627,10 @@ unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
|
||||
}
|
||||
|
||||
// Create the base instruction, then add the operands.
|
||||
unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
||||
.addReg(Op0, getKillRegState(Op0IsKill))
|
||||
.addReg(Op1, getKillRegState(Op1IsKill))
|
||||
.addReg(ZReg, getKillRegState(true));
|
||||
|
||||
return ResultReg;
|
||||
const TargetRegisterClass *RC =
|
||||
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
return FastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
|
||||
/*IsKill=*/ZReg, true);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
@ -2625,15 +2638,9 @@ unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
if (RetVT != MVT::i64)
|
||||
return 0;
|
||||
|
||||
// Create the base instruction, then add the operands.
|
||||
unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SMADDLrrr),
|
||||
ResultReg)
|
||||
.addReg(Op0, getKillRegState(Op0IsKill))
|
||||
.addReg(Op1, getKillRegState(Op1IsKill))
|
||||
.addReg(AArch64::XZR, getKillRegState(true));
|
||||
|
||||
return ResultReg;
|
||||
return FastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
|
||||
Op0, Op0IsKill, Op1, Op1IsKill,
|
||||
AArch64::XZR, /*IsKill=*/true);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
@ -2641,15 +2648,9 @@ unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
if (RetVT != MVT::i64)
|
||||
return 0;
|
||||
|
||||
// Create the base instruction, then add the operands.
|
||||
unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::UMADDLrrr),
|
||||
ResultReg)
|
||||
.addReg(Op0, getKillRegState(Op0IsKill))
|
||||
.addReg(Op1, getKillRegState(Op1IsKill))
|
||||
.addReg(AArch64::XZR, getKillRegState(true));
|
||||
|
||||
return ResultReg;
|
||||
return FastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
|
||||
Op0, Op0IsKill, Op1, Op1IsKill,
|
||||
AArch64::XZR, /*IsKill=*/true);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_LSL_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
@ -2667,9 +2668,9 @@ unsigned AArch64FastISel::Emit_LSL_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
Opc = AArch64::UBFMXri; ImmR = -Shift % 64; ImmS = 63 - Shift; break;
|
||||
}
|
||||
|
||||
RetVT.SimpleTy = std::max(MVT::i32, RetVT.SimpleTy);
|
||||
return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, ImmR,
|
||||
ImmS);
|
||||
const TargetRegisterClass *RC =
|
||||
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_LSR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
@ -2683,9 +2684,9 @@ unsigned AArch64FastISel::Emit_LSR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
case MVT::i64: Opc = AArch64::UBFMXri; ImmS = 63; break;
|
||||
}
|
||||
|
||||
RetVT.SimpleTy = std::max(MVT::i32, RetVT.SimpleTy);
|
||||
return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, Shift,
|
||||
ImmS);
|
||||
const TargetRegisterClass *RC =
|
||||
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, Shift, ImmS);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_ASR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
@ -2699,9 +2700,9 @@ unsigned AArch64FastISel::Emit_ASR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
case MVT::i64: Opc = AArch64::SBFMXri; ImmS = 63; break;
|
||||
}
|
||||
|
||||
RetVT.SimpleTy = std::max(MVT::i32, RetVT.SimpleTy);
|
||||
return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, Shift,
|
||||
ImmS);
|
||||
const TargetRegisterClass *RC =
|
||||
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, Shift, ImmS);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
||||
@ -2760,13 +2761,9 @@ unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
||||
SrcReg = Src64;
|
||||
}
|
||||
|
||||
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
||||
.addReg(SrcReg)
|
||||
.addImm(0)
|
||||
.addImm(Imm);
|
||||
|
||||
return ResultReg;
|
||||
const TargetRegisterClass *RC =
|
||||
(DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
return FastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
||||
@ -2843,22 +2840,23 @@ bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
|
||||
unsigned Src0Reg = getRegForValue(I->getOperand(0));
|
||||
if (!Src0Reg)
|
||||
return false;
|
||||
bool Src0IsKill = hasTrivialKill(I->getOperand(0));
|
||||
|
||||
unsigned Src1Reg = getRegForValue(I->getOperand(1));
|
||||
if (!Src1Reg)
|
||||
return false;
|
||||
bool Src1IsKill = hasTrivialKill(I->getOperand(1));
|
||||
|
||||
unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
|
||||
.addReg(Src0Reg)
|
||||
.addReg(Src1Reg);
|
||||
const TargetRegisterClass *RC =
|
||||
(DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
unsigned QuotReg = FastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
|
||||
Src1Reg, /*IsKill=*/false);
|
||||
assert(QuotReg && "Unexpected DIV instruction emission failure.");
|
||||
// The remainder is computed as numerator - (quotient * denominator) using the
|
||||
// MSUB instruction.
|
||||
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
|
||||
.addReg(QuotReg)
|
||||
.addReg(Src1Reg)
|
||||
.addReg(Src0Reg);
|
||||
unsigned ResultReg = FastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
|
||||
Src1Reg, Src1IsKill, Src0Reg,
|
||||
Src0IsKill);
|
||||
UpdateValueMap(I, ResultReg);
|
||||
return true;
|
||||
}
|
||||
@ -2948,12 +2946,19 @@ bool AArch64FastISel::SelectBitCast(const Instruction *I) {
|
||||
else
|
||||
return false;
|
||||
|
||||
const TargetRegisterClass *RC = nullptr;
|
||||
switch (RetVT.SimpleTy) {
|
||||
default: llvm_unreachable("Unexpected value type.");
|
||||
case MVT::i32: RC = &AArch64::GPR32RegClass; break;
|
||||
case MVT::i64: RC = &AArch64::GPR64RegClass; break;
|
||||
case MVT::f32: RC = &AArch64::FPR32RegClass; break;
|
||||
case MVT::f64: RC = &AArch64::FPR64RegClass; break;
|
||||
}
|
||||
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
||||
if (!Op0Reg)
|
||||
return false;
|
||||
bool Op0IsKill = hasTrivialKill(I->getOperand(0));
|
||||
unsigned ResultReg = FastEmitInst_r(Opc, TLI.getRegClassFor(RetVT),
|
||||
Op0Reg, Op0IsKill);
|
||||
unsigned ResultReg = FastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
|
||||
|
||||
if (!ResultReg)
|
||||
return false;
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -march=arm64 -O0 < %s | FileCheck %s
|
||||
; RUN: llc -march=arm64 -O3 < %s | FileCheck %s
|
||||
; RUN: llc -march=arm64 -O0 -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -march=arm64 -O3 -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
@.str = private unnamed_addr constant [9 x i8] c"%lf %lu\0A\00", align 1
|
||||
@.str1 = private unnamed_addr constant [8 x i8] c"%lf %u\0A\00", align 1
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
|
||||
; RUN: llc -O0 -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
; The following 2 test cases test shufflevector with beginning UNDEF mask.
|
||||
define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
|
||||
|
@ -1,7 +1,6 @@
|
||||
; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
|
||||
; RUN: llc < %s -O0 | FileCheck -check-prefix=FAST %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false < %s | FileCheck %s
|
||||
; RUN: llc -O0 -mtriple=arm64-apple-darwin < %s | FileCheck --check-prefix=FAST %s
|
||||
; REQUIRES: asserts
|
||||
target triple = "arm64-apple-darwin"
|
||||
|
||||
; rdar://9932559
|
||||
define i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext %a5, i64 %a6, i64 %a7, i64 %a8, i8 signext %b1, i16 signext %b2, i8 signext %b3, i8 signext %b4) nounwind readnone noinline {
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
@sortlist = common global [5001 x i32] zeroinitializer, align 16
|
||||
@sortlist2 = common global [5001 x i64] zeroinitializer, align 16
|
||||
|
@ -1,5 +1,5 @@
|
||||
; This test should cause the TargetMaterializeAlloca to be invoked
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
%struct.S1Ty = type { i64 }
|
||||
%struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define void @branch1() nounwind uwtable ssp {
|
||||
%x = alloca i32, align 4
|
||||
|
@ -1,6 +1,6 @@
|
||||
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE
|
||||
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
|
||||
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE
|
||||
; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE
|
||||
|
||||
define void @call0() nounwind {
|
||||
entry:
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s
|
||||
|
||||
;; Test various conversions.
|
||||
define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
|
||||
entry:
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
; Test load/store of global value from global offset table.
|
||||
@seed = common global i64 0, align 8
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
|
||||
entry:
|
||||
|
@ -1,10 +1,10 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
@fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8
|
||||
|
||||
define i32 @fn(i32 %target) nounwind {
|
||||
entry:
|
||||
; CHECK: @fn
|
||||
; CHECK-LABEL: fn
|
||||
%retval = alloca i32, align 4
|
||||
%target.addr = alloca i32, align 4
|
||||
store i32 %target, i32* %target.addr, align 4
|
||||
@ -29,8 +29,8 @@ return: ; preds = %ONE, %ZERO
|
||||
ret i32 %2
|
||||
|
||||
indirectgoto: ; preds = %entry
|
||||
; CHECK: ldr x0, [sp]
|
||||
; CHECK: br x0
|
||||
; CHECK: ldr [[REG:x[0-9]+]], [sp]
|
||||
; CHECK-NEXT: br [[REG]]
|
||||
%indirect.goto.dest = phi i8* [ %1, %entry ]
|
||||
indirectbr i8* %indirect.goto.dest, [label %ZERO, label %ONE]
|
||||
}
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios | FileCheck %s --check-prefix=ARM64
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64
|
||||
|
||||
@message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16
|
||||
@temp = common global [80 x i8] zeroinitializer, align 16
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc -mtriple=arm64-apple-ios -O0 %s -o - | FileCheck %s
|
||||
; RUN: llc -O0 -verify-machineinstrs -mtriple=aarch64-apple-ios < %s | FileCheck %s
|
||||
|
||||
; Fast-isel can't do vector conversions yet, but it was emitting some highly
|
||||
; suspect UCVTFUWDri MachineInstrs.
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
|
||||
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
|
||||
; REQUIRES: asserts
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
;; Test returns.
|
||||
define void @t0() nounwind ssp {
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define i32 @t1(i32 %c) nounwind readnone {
|
||||
entry:
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define void @store_i8(i8* %a) {
|
||||
; CHECK-LABEL: store_i8
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
||||
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
|
||||
define void @t0(i32 %a) nounwind {
|
||||
entry:
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
|
||||
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort < %s | FileCheck %s
|
||||
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
;
|
||||
; Get the actual value of the overflow bit.
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
|
||||
|
||||
; Load / Store Base Register only
|
||||
define zeroext i1 @load_breg_i1(i1* %a) {
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
; Test if the BBs are reordred according to their branch weights.
|
||||
define i64 @branch_weights_test(i64 %a, i64 %b) {
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc -fast-isel -fast-isel-abort < %s | FileCheck %s
|
||||
; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64-linux-gnu"
|
||||
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc -fast-isel -fast-isel-abort -mtriple=aarch64 -o - %s | FileCheck %s
|
||||
; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64 < %s | FileCheck %s
|
||||
|
||||
@var8 = global i8 0
|
||||
@var16 = global i16 0
|
||||
@ -7,7 +7,7 @@
|
||||
|
||||
define void @test_mul8(i8 %lhs, i8 %rhs) {
|
||||
; CHECK-LABEL: test_mul8:
|
||||
; CHECK: mul w0, w0, w1
|
||||
; CHECK: mul {{w[0-9]+}}, w0, w1
|
||||
; %lhs = load i8* @var8
|
||||
; %rhs = load i8* @var8
|
||||
%prod = mul i8 %lhs, %rhs
|
||||
@ -17,7 +17,7 @@ define void @test_mul8(i8 %lhs, i8 %rhs) {
|
||||
|
||||
define void @test_mul16(i16 %lhs, i16 %rhs) {
|
||||
; CHECK-LABEL: test_mul16:
|
||||
; CHECK: mul w0, w0, w1
|
||||
; CHECK: mul {{w[0-9]+}}, w0, w1
|
||||
%prod = mul i16 %lhs, %rhs
|
||||
store i16 %prod, i16* @var16
|
||||
ret void
|
||||
@ -25,7 +25,7 @@ define void @test_mul16(i16 %lhs, i16 %rhs) {
|
||||
|
||||
define void @test_mul32(i32 %lhs, i32 %rhs) {
|
||||
; CHECK-LABEL: test_mul32:
|
||||
; CHECK: mul w0, w0, w1
|
||||
; CHECK: mul {{w[0-9]+}}, w0, w1
|
||||
%prod = mul i32 %lhs, %rhs
|
||||
store i32 %prod, i32* @var32
|
||||
ret void
|
||||
@ -33,7 +33,7 @@ define void @test_mul32(i32 %lhs, i32 %rhs) {
|
||||
|
||||
define void @test_mul64(i64 %lhs, i64 %rhs) {
|
||||
; CHECK-LABEL: test_mul64:
|
||||
; CHECK: mul x0, x0, x1
|
||||
; CHECK: mul {{x[0-9]+}}, x0, x1
|
||||
%prod = mul i64 %lhs, %rhs
|
||||
store i64 %prod, i64* @var64
|
||||
ret void
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: lsl_i8
|
||||
; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define float @test_sqrt_f32(float %a) {
|
||||
; CHECK-LABEL: test_sqrt_f32
|
||||
|
@ -1,5 +1,5 @@
|
||||
; RUN: llc -mtriple=arm64-apple-ios7.0 < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=arm64-apple-ios7.0 -fast-isel -fast-isel-abort < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
|
||||
|
||||
define i8* @test_frameaddress0() nounwind {
|
||||
entry:
|
||||
|
Loading…
Reference in New Issue
Block a user