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R600/SI: Fix simple-loop.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226596 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -99,7 +99,9 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
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ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
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BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
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.addReg(ScratchOffsetPreloadReg)
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.addFrameIndex(ScratchOffsetFI);
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.addFrameIndex(ScratchOffsetFI)
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.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
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.addReg(AMDGPU::SGPR0, RegState::Undef);
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}
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@ -116,7 +118,8 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
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MachineBasicBlock &MBB = *BI;
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// Add the scratch offset reg as a live-in so that the register scavenger
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// doesn't re-use it.
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if (!MBB.isLiveIn(ScratchOffsetReg))
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if (!MBB.isLiveIn(ScratchOffsetReg) &&
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ScratchOffsetReg != AMDGPU::NoRegister)
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MBB.addLiveIn(ScratchOffsetReg);
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RS.enterBasicBlock(&MBB);
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@ -173,8 +176,8 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
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BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
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ScratchOffsetReg)
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.addFrameIndex(ScratchOffsetFI)
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.addReg(AMDGPU::NoRegister)
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.addReg(AMDGPU::NoRegister);
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.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
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.addReg(AMDGPU::SGPR0, RegState::Undef);
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} else if (!MBB.isLiveIn(ScratchOffsetReg)) {
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MBB.addLiveIn(ScratchOffsetReg);
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}
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@ -191,6 +194,7 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
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MI.getOperand(2).setIsUndef(false);
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MI.getOperand(3).setReg(ScratchOffsetReg);
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MI.getOperand(3).setIsUndef(false);
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MI.getOperand(3).setIsKill(false);
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MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
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MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
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MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
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@ -142,7 +142,7 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
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.addReg(SubReg, getDefRegState(IsLoad))
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.addReg(ScratchRsrcReg, getKillRegState(IsKill))
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.addImm(Offset)
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.addReg(SOffset, getKillRegState(IsKill))
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.addReg(SOffset)
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.addImm(0) // glc
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.addImm(0) // slc
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.addImm(0) // tfe
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@ -1,4 +1,3 @@
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; XFAIL: *
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; RUN: llc -O0 -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test_loop:
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