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Basic non-power-of-2 vector support

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44181 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2007-11-15 21:15:26 +00:00
parent 4e1a0e386c
commit 5db1afb462
6 changed files with 320 additions and 319 deletions
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564
lib/AsmParser/llvmAsmParser.cpp.cvs
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File diff suppressed because it is too large Load Diff

4
lib/AsmParser/llvmAsmParser.h.cvs
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@ -338,7 +338,7 @@
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
typedef union YYSTYPE typedef union YYSTYPE
#line 968 "/home/asl/proj/llvm/src/lib/AsmParser/llvmAsmParser.y" #line 968 "/llvm/lib/AsmParser/llvmAsmParser.y"
{ {
llvm::Module *ModuleVal; llvm::Module *ModuleVal;
llvm::Function *FunctionVal; llvm::Function *FunctionVal;
@ -385,7 +385,7 @@ typedef union YYSTYPE
llvm::ICmpInst::Predicate IPredicate; llvm::ICmpInst::Predicate IPredicate;
llvm::FCmpInst::Predicate FPredicate; llvm::FCmpInst::Predicate FPredicate;
} }
/* Line 1489 of yacc.c. */ /* Line 1529 of yacc.c. */
#line 390 "llvmAsmParser.tab.h" #line 390 "llvmAsmParser.tab.h"
YYSTYPE; YYSTYPE;
# define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define yystype YYSTYPE /* obsolescent; will be withdrawn */

2
lib/AsmParser/llvmAsmParser.y
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@ -1422,8 +1422,6 @@ Types
GEN_ERROR("Unsigned result not equal to signed result"); GEN_ERROR("Unsigned result not equal to signed result");
if (!ElemTy->isFloatingPoint() && !ElemTy->isInteger()) if (!ElemTy->isFloatingPoint() && !ElemTy->isInteger())
GEN_ERROR("Element type of a VectorType must be primitive"); GEN_ERROR("Element type of a VectorType must be primitive");
if (!isPowerOf2_32($2))
GEN_ERROR("Vector length should be a power of 2");
$$ = new PATypeHolder(HandleUpRefs(VectorType::get(*$4, (unsigned)$2))); $$ = new PATypeHolder(HandleUpRefs(VectorType::get(*$4, (unsigned)$2)));
delete $4; delete $4;
CHECK_FOR_ERROR CHECK_FOR_ERROR

2
lib/AsmParser/llvmAsmParser.y.cvs
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@ -1422,8 +1422,6 @@ Types
GEN_ERROR("Unsigned result not equal to signed result"); GEN_ERROR("Unsigned result not equal to signed result");
if (!ElemTy->isFloatingPoint() && !ElemTy->isInteger()) if (!ElemTy->isFloatingPoint() && !ElemTy->isInteger())
GEN_ERROR("Element type of a VectorType must be primitive"); GEN_ERROR("Element type of a VectorType must be primitive");
if (!isPowerOf2_32($2))
GEN_ERROR("Vector length should be a power of 2");
$$ = new PATypeHolder(HandleUpRefs(VectorType::get(*$4, (unsigned)$2))); $$ = new PATypeHolder(HandleUpRefs(VectorType::get(*$4, (unsigned)$2)));
delete $4; delete $4;
CHECK_FOR_ERROR CHECK_FOR_ERROR

64
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -2158,7 +2158,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break; break;
} else { } else {
SplitVectorOp(Node->getOperand(1), Lo, Hi); SplitVectorOp(Node->getOperand(1), Lo, Hi);
IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
MVT::getSizeInBits(EVT)/8;
} }
} else { } else {
ExpandOp(Node->getOperand(1), Lo, Hi); ExpandOp(Node->getOperand(1), Lo, Hi);
@ -6226,9 +6227,14 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
SDNode *Node = Op.Val; SDNode *Node = Op.Val;
unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
assert(NumElements > 1 && "Cannot split a single element vector!"); assert(NumElements > 1 && "Cannot split a single element vector!");
unsigned NewNumElts = NumElements/2;
MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
// See if we already split it. // See if we already split it.
std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
@ -6253,25 +6259,27 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
SplitVectorOp(Node->getOperand(0), Lo, Hi); SplitVectorOp(Node->getOperand(0), Lo, Hi);
unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
SDOperand ScalarOp = Node->getOperand(1); SDOperand ScalarOp = Node->getOperand(1);
if (Index < NewNumElts) if (Index < NewNumElts_Lo)
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp, Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
DAG.getConstant(Index, TLI.getPointerTy())); DAG.getConstant(Index, TLI.getPointerTy()));
else else
Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp, Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
DAG.getConstant(Index - NewNumElts, TLI.getPointerTy())); DAG.getConstant(Index - NewNumElts_Lo,
TLI.getPointerTy()));
break; break;
} }
case ISD::BUILD_VECTOR: { case ISD::BUILD_VECTOR: {
SmallVector<SDOperand, 8> LoOps(Node->op_begin(), SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumElts); Node->op_begin()+NewNumElts_Lo);
Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
Node->op_end()); Node->op_end());
Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
break; break;
} }
case ISD::CONCAT_VECTORS: { case ISD::CONCAT_VECTORS: {
// FIXME: Handle non-power-of-two vectors?
unsigned NewNumSubvectors = Node->getNumOperands() / 2; unsigned NewNumSubvectors = Node->getNumOperands() / 2;
if (NewNumSubvectors == 1) { if (NewNumSubvectors == 1) {
Lo = Node->getOperand(0); Lo = Node->getOperand(0);
@ -6279,11 +6287,11 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
} else { } else {
SmallVector<SDOperand, 8> LoOps(Node->op_begin(), SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
Node->op_begin()+NewNumSubvectors); Node->op_begin()+NewNumSubvectors);
Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
Node->op_end()); Node->op_end());
Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
} }
break; break;
} }
@ -6298,12 +6306,12 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
// Handle a vector merge. // Handle a vector merge.
SDOperand CL, CH; SDOperand CL, CH;
SplitVectorOp(Cond, CL, CH); SplitVectorOp(Cond, CL, CH);
Lo = DAG.getNode(Node->getOpcode(), NewVT, CL, LL, RL); Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
Hi = DAG.getNode(Node->getOpcode(), NewVT, CH, LH, RH); Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
} else { } else {
// Handle a simple select with vector operands. // Handle a simple select with vector operands.
Lo = DAG.getNode(Node->getOpcode(), NewVT, Cond, LL, RL); Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
Hi = DAG.getNode(Node->getOpcode(), NewVT, Cond, LH, RH); Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
} }
break; break;
} }
@ -6324,16 +6332,16 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
SplitVectorOp(Node->getOperand(0), LL, LH); SplitVectorOp(Node->getOperand(0), LL, LH);
SplitVectorOp(Node->getOperand(1), RL, RH); SplitVectorOp(Node->getOperand(1), RL, RH);
Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
break; break;
} }
case ISD::FPOWI: { case ISD::FPOWI: {
SDOperand L, H; SDOperand L, H;
SplitVectorOp(Node->getOperand(0), L, H); SplitVectorOp(Node->getOperand(0), L, H);
Lo = DAG.getNode(Node->getOpcode(), NewVT, L, Node->getOperand(1)); Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
Hi = DAG.getNode(Node->getOpcode(), NewVT, H, Node->getOperand(1)); Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
break; break;
} }
case ISD::CTTZ: case ISD::CTTZ:
@ -6347,8 +6355,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
SDOperand L, H; SDOperand L, H;
SplitVectorOp(Node->getOperand(0), L, H); SplitVectorOp(Node->getOperand(0), L, H);
Lo = DAG.getNode(Node->getOpcode(), NewVT, L); Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
Hi = DAG.getNode(Node->getOpcode(), NewVT, H); Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
break; break;
} }
case ISD::LOAD: { case ISD::LOAD: {
@ -6360,13 +6368,13 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
unsigned Alignment = LD->getAlignment(); unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile(); bool isVolatile = LD->isVolatile();
Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
getIntPtrConstant(IncrementSize)); getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize; SVOffset += IncrementSize;
Alignment = MinAlign(Alignment, IncrementSize); Alignment = MinAlign(Alignment, IncrementSize);
Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
// Build a factor node to remember that this load is independent of the // Build a factor node to remember that this load is independent of the
// other one. // other one.
@ -6394,8 +6402,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
} }
// Split the vector and convert each of the pieces now. // Split the vector and convert each of the pieces now.
SplitVectorOp(InOp, Lo, Hi); SplitVectorOp(InOp, Lo, Hi);
Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
break; break;
} }
} }

1
lib/VMCore/Type.cpp
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@ -1209,7 +1209,6 @@ static ManagedStatic<TypeMap<VectorValType, VectorType> > VectorTypes;
VectorType *VectorType::get(const Type *ElementType, unsigned NumElements) { VectorType *VectorType::get(const Type *ElementType, unsigned NumElements) {
assert(ElementType && "Can't get vector of null types!"); assert(ElementType && "Can't get vector of null types!");
assert(isPowerOf2_32(NumElements) && "Vector length should be a power of 2!");
VectorValType PVT(ElementType, NumElements); VectorValType PVT(ElementType, NumElements);
VectorType *PT = VectorTypes->get(PVT); VectorType *PT = VectorTypes->get(PVT);