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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding doubleword load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224787 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
3c3fc28384
commit
5dbd280542
@ -404,7 +404,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
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dl, PointerTy,
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TargAddr);
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// Figure out base + offset opcode
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if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
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if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io;
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else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
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else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
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else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
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@ -597,7 +597,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::POST_LDrid;
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else
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Opcode = Hexagon::LDrid;
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Opcode = Hexagon::L2_loadrd_io;
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} else if (LoadedVT == MVT::i32) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = Hexagon::POST_LDriw;
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@ -79,7 +79,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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switch (MI->getOpcode()) {
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default: break;
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case Hexagon::L2_loadri_io:
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case Hexagon::LDrid:
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case Hexagon::L2_loadrd_io:
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case Hexagon::L2_loadrh_io:
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case Hexagon::L2_loadrb_io:
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case Hexagon::L2_loadrub_io:
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@ -536,7 +536,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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} else if (RC == &Hexagon::DoubleRegsRegClass) {
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BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
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BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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} else if (RC == &Hexagon::PredRegsRegClass) {
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BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
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@ -670,8 +670,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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case Hexagon::STrib_nv_V4:
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return isUInt<6>(MI->getOperand(1).getImm());
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case Hexagon::LDrid:
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case Hexagon::LDrid_indexed:
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case Hexagon::L2_loadrd_io:
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return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
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case Hexagon::L2_loadri_io:
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@ -1110,8 +1109,7 @@ isValidOffset(const int Opcode, const int Offset) const {
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return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
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(Offset <= Hexagon_MEMW_OFFSET_MAX);
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case Hexagon::LDrid:
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case Hexagon::LDrid_indexed:
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case Hexagon::L2_loadrd_io:
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case Hexagon::LDrid_f:
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case Hexagon::STrid:
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case Hexagon::STrid_indexed:
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@ -1346,10 +1344,8 @@ isConditionalLoad (const MachineInstr* MI) const {
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switch (MI->getOpcode())
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{
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default: return false;
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case Hexagon::LDrid_cPt :
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case Hexagon::LDrid_cNotPt :
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case Hexagon::LDrid_indexed_cPt :
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case Hexagon::LDrid_indexed_cNotPt :
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case Hexagon::L2_ploadrdt_io :
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case Hexagon::L2_ploadrdf_io:
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case Hexagon::L2_ploadrit_io:
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case Hexagon::L2_ploadrif_io:
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case Hexagon::L2_ploadrht_io:
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@ -1555,6 +1555,9 @@ let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
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let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in
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defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
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let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
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defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
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///
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// Load -- MEMri operand
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multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
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@ -1594,11 +1597,6 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
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}
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}
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let addrMode = BaseImmOffset, isMEMri = "true" in {
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let accessSize = DoubleWordAccess in
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defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;
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}
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def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
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(L2_loadrb_io AddrFI:$addr, 0) >;
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@ -1615,7 +1613,7 @@ def : Pat < (i32 (load ADDRriS11_2:$addr)),
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(L2_loadri_io AddrFI:$addr, 0) >;
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def : Pat < (i64 (load ADDRriS11_3:$addr)),
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(LDrid ADDRriS11_3:$addr) >;
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(L2_loadrd_io AddrFI:$addr, 0) >;
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// Load - Base with Immediate offset addressing mode
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@ -1658,12 +1656,6 @@ multiclass LD_Idxd2<string mnemonic, string CextOp, RegisterClass RC,
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}
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}
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let addrMode = BaseImmOffset in {
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let accessSize = DoubleWordAccess in
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defm LDrid_indexed: LD_Idxd2 <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,
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14, 9>, AddrModeRel;
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}
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let AddedComplexity = 20 in {
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def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
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(L2_loadrb_io IntRegs:$src1, s11_0ExtPred:$offset) >;
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@ -1681,7 +1673,7 @@ def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
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(L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset) >;
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def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
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(LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;
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(L2_loadrd_io IntRegs:$src1, s11_3ExtPred:$offset) >;
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}
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//===----------------------------------------------------------------------===//
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@ -3664,10 +3656,10 @@ def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),
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// 64 bit atomic load
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def : Pat<(atomic_load_64 ADDRriS11_3:$src1),
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(i64 (LDrid ADDRriS11_3:$src1))>;
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(i64 (L2_loadrd_io AddrFI:$src1, 0))>;
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def : Pat<(atomic_load_64 (add (i32 IntRegs:$src1), s11_3ImmPred:$offset)),
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(i64 (LDrid_indexed (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
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(i64 (L2_loadrd_io (i32 IntRegs:$src1), s11_3ImmPred:$offset))>;
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def : Pat<(atomic_store_8 ADDRriS11_0:$src2, (i32 IntRegs:$src1)),
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@ -160,14 +160,14 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// r0 = add(r30, #10000)
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// r0 = memw(r0)
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if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||
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(MI.getOpcode() == Hexagon::LDrid) ||
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(MI.getOpcode() == Hexagon::L2_loadrd_io) ||
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(MI.getOpcode() == Hexagon::L2_loadrh_io) ||
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(MI.getOpcode() == Hexagon::L2_loadruh_io) ||
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(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
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(MI.getOpcode() == Hexagon::L2_loadrub_io) ||
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(MI.getOpcode() == Hexagon::LDriw_f) ||
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(MI.getOpcode() == Hexagon::LDrid_f)) {
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unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
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unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
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getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
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MI.getOperand(0).getReg();
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@ -1,5 +1,15 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x70 0xd8 0xd5 0x41
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# CHECK: if (p3) r17:16 = memd(r21 + #24)
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0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24)
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0x70 0xd8 0xd5 0x45
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# CHECK: if (!p3) r17:16 = memd(r21 + #24)
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0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24)
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0xf1 0xc3 0x15 0x91
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# CHECK: r17 = memb(r21 + #31)
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0x91 0xdd 0x15 0x41
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