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Dump LIS before regalloc. MI sched changes them.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-07-25 07:26:26 +00:00
parent 27ce44d3b4
commit 5dca613978
2 changed files with 4 additions and 2 deletions
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4
lib/CodeGen/MachineScheduler.cpp
View File

@ -204,7 +204,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
if (VerifyScheduling) {
DEBUG(LIS->print(dbgs()));
DEBUG(LIS->dump());
MF->verify(this, "Before machine scheduling.");
}
RegClassInfo->runOnMachineFunction(*MF);
@ -294,7 +294,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
Scheduler->finishBlock();
}
Scheduler->finalizeSchedule();
DEBUG(LIS->print(dbgs()));
DEBUG(LIS->dump());
if (VerifyScheduling)
MF->verify(this, "After machine scheduling.");
return true;

2
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -1786,6 +1786,8 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
SpillPlacer = &getAnalysis<SpillPlacement>();
DebugVars = &getAnalysis<LiveDebugVariables>();
DEBUG(LIS->dump());
SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
ExtraRegInfo.clear();