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[Hexagon] Adding asrh instruction, removing unused multiclasses.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
2014-11-24 18:04:42 +00:00
parent c1c7be0928
commit 5de3458c18
3 changed files with 17 additions and 40 deletions
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9
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@@ -714,7 +714,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
return isInt<8>(MI->getOperand(2).getImm());
case Hexagon::A2_aslh:
case Hexagon::ASRH:
case Hexagon::A2_asrh:
case Hexagon::A2_sxtb:
case Hexagon::A2_sxth:
case Hexagon::A2_zxtb:
@@ -1307,6 +1307,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A4_paslhfnew:
case Hexagon::A4_paslht:
case Hexagon::A4_paslhtnew:
case Hexagon::A4_pasrhf:
case Hexagon::A4_pasrhfnew:
case Hexagon::A4_pasrht:
case Hexagon::A4_pasrhtnew:
case Hexagon::A2_porf:
case Hexagon::A2_porfnew:
case Hexagon::A2_port:
@@ -1340,9 +1344,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::COMBINE_rr_cPt:
case Hexagon::COMBINE_rr_cNotPt:
return true;
case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4:
return QRI.Subtarget.hasV4TOps();
}
}