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Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35332 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2387,14 +2387,23 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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if (RegVT == ValueVT)
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return Val;
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if (MVT::isVector(RegVT)) {
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assert(ValueVT == MVT::Vector && "Unknown vector conversion!");
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return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
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DAG.getConstant(MVT::getVectorNumElements(RegVT),
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MVT::i32),
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DAG.getValueType(MVT::getVectorBaseType(RegVT)));
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}
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if (MVT::isInteger(RegVT)) {
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if (ValueVT < RegVT)
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return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
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else
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return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
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} else {
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
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}
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assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT));
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
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}
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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@ -2407,7 +2416,10 @@ void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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// If there is a single register and the types differ, this must be
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// a promotion.
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if (RegVT != ValueVT) {
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if (MVT::isInteger(RegVT)) {
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if (MVT::isVector(RegVT)) {
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assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?");
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Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
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} else if (MVT::isInteger(RegVT)) {
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if (RegVT < ValueVT)
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Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
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else
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@ -3424,7 +3436,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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// If this value was promoted, truncate it down.
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if (ResVal.getValueType() != VT) {
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if (VT == MVT::Vector) {
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// Insert a VBITCONVERT to convert from the packed result type to the
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// Insert a VBIT_CONVERT to convert from the packed result type to the
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// MVT::Vector type.
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unsigned NumElems = cast<VectorType>(RetTy)->getNumElements();
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const Type *EltTy = cast<VectorType>(RetTy)->getElementType();
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