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Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-06-02 01:03:14 +00:00
parent f876bf81df
commit 5e06903e66
3 changed files with 28 additions and 36 deletions
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33
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -135,24 +135,25 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
} }
} }
// Addresses of the form FI+const or FI|const
if (CurDAG->isBaseWithConstantOffset(Addr)) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
if (isInt<16>(CN->getSExtValue())) {
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
(Addr.getOperand(0)))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
else
Base = Addr.getOperand(0);
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}
// Operand is a result from an ADD. // Operand is a result from an ADD.
if (Addr.getOpcode() == ISD::ADD) { if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
if (isInt<16>(CN->getSExtValue())) {
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
(Addr.getOperand(0))) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
} else {
Base = Addr.getOperand(0);
}
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
return true;
}
}
// When loading from constant pools, load the lower address part in // When loading from constant pools, load the lower address part in
// the instruction itself. Example, instead of: // the instruction itself. Example, instead of:
// lui $2, %hi($CPI1_0) // lui $2, %hi($CPI1_0)

2
test/CodeGen/Mips/largeimmprinting.ll
View File

@ -8,7 +8,7 @@ define void @f() nounwind {
entry: entry:
; CHECK: lui $at, 65534 ; CHECK: lui $at, 65534
; CHECK: addu $at, $sp, $at ; CHECK: addu $at, $sp, $at
; CHECK: addiu $sp, $at, -24 ; CHECK: addiu $sp, $at, -16
; CHECK: .cprestore 65536 ; CHECK: .cprestore 65536
%agg.tmp = alloca %struct.S1, align 1 %agg.tmp = alloca %struct.S1, align 1

29
test/CodeGen/Mips/o32_cc_byval.ll
View File

@ -10,18 +10,16 @@
define void @f1() nounwind { define void @f1() nounwind {
entry: entry:
; CHECK: lw $[[R0:[0-9]+]], %got(f1.s1)($gp) ; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp)
; CHECK: addiu $[[R1:[0-9]+]], $sp, 16 ; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
; CHECK: addiu $[[R0:[0-9]+]], $[[R0]], %lo(f1.s1)
; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) ; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) ; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) ; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: ori $[[R8:[0-9]+]], $[[R1]], 4
; CHECK: sw $[[R2]], 16($sp) ; CHECK: sw $[[R2]], 16($sp)
; CHECK: sw $[[R7]], 0($[[R8]]) ; CHECK: sw $[[R7]], 20($sp)
; CHECK: sw $[[R3]], 24($sp) ; CHECK: sw $[[R3]], 24($sp)
; CHECK: sw $[[R4]], 28($sp) ; CHECK: sw $[[R4]], 28($sp)
; CHECK: sw $[[R5]], 32($sp) ; CHECK: sw $[[R5]], 32($sp)
@ -46,14 +44,11 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval)
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry: entry:
; CHECK: addiu $sp, $sp, -56 ; CHECK: addiu $sp, $sp, -56
; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
; CHECK: ori $[[R1:[0-9]+]], $[[R0]], 4
; CHECK: ori $[[R0:[0-9]+]], $[[R0]], 2
; CHECK: sw $6, 64($sp) ; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 0($[[R1]]) ; CHECK: sw $7, 68($sp)
; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp) ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
; CHECK: lw $[[R2:[0-9]+]], 0($[[R1]]) ; CHECK: lw $[[R2:[0-9]+]], 68($sp)
; CHECK: lh $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: lh $[[R1:[0-9]+]], 66($sp)
; CHECK: lb $[[R0:[0-9]+]], 64($sp) ; CHECK: lb $[[R0:[0-9]+]], 64($sp)
; CHECK: lw $[[R3:[0-9]+]], 72($sp) ; CHECK: lw $[[R3:[0-9]+]], 72($sp)
; CHECK: lw $[[R4:[0-9]+]], 76($sp) ; CHECK: lw $[[R4:[0-9]+]], 76($sp)
@ -86,10 +81,8 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float)
define void @f3(%struct.S2* nocapture byval %s2) nounwind { define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry: entry:
; CHECK: addiu $sp, $sp, -56 ; CHECK: addiu $sp, $sp, -56
; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
; CHECK: ori $[[R0:[0-9]+]], $[[R0]], 4
; CHECK: sw $4, 56($sp) ; CHECK: sw $4, 56($sp)
; CHECK: sw $5, 0($[[R0]]) ; CHECK: sw $5, 60($sp)
; CHECK: sw $6, 64($sp) ; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp) ; CHECK: sw $7, 68($sp)
; CHECK: lw $[[R0:[0-9]+]], 68($sp) ; CHECK: lw $[[R0:[0-9]+]], 68($sp)
@ -107,14 +100,12 @@ entry:
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry: entry:
; CHECK: addiu $sp, $sp, -56 ; CHECK: addiu $sp, $sp, -56
; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
; CHECK: ori $[[R2:[0-9]+]], $[[R0]], 4
; CHECK: sw $5, 60($sp) ; CHECK: sw $5, 60($sp)
; CHECK: sw $6, 64($sp) ; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 0($[[R2]]) ; CHECK: sw $7, 68($sp)
; CHECK: lw $[[R1:[0-9]+]], 88($sp) ; CHECK: lw $[[R1:[0-9]+]], 88($sp)
; CHECK: lb $[[R0:[0-9]+]], 60($sp) ; CHECK: lb $[[R0:[0-9]+]], 60($sp)
; CHECK: lw $4, 0($[[R2]]) ; CHECK: lw $4, 68($sp)
; CHECK: sw $[[R1]], 24($sp) ; CHECK: sw $[[R1]], 24($sp)
; CHECK: sw $[[R0]], 32($sp) ; CHECK: sw $[[R0]], 32($sp)