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[X86] Improve a dag-combine that handles a vector extract -> zext sequence.
The current DAG combine turns a sequence of extracts from <4 x i32> followed by zexts into a store followed by scalar loads. According to measurements by Martin Krastev (see PR 21269) for x86-64, a sequence of an extract, movs and shifts gives better performance. However, for 32-bit x86, the previous sequence still seems better. Differential Revision: http://reviews.llvm.org/D6501 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223360 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Kuperstein
parent
996b683a9f
commit
5e343e6fd0
@ -22558,7 +22558,9 @@ static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
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/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
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/// generation and convert it from being a bunch of shuffles and extracts
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/// to a simple store and scalar loads to extract the elements.
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/// into a somewhat faster sequence. For i686, the best sequence is apparently
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/// storing the value and loading scalars back, while for x64 we should
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/// use 64-bit extracts and shifts.
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static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI) {
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SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
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@ -22617,36 +22619,61 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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// Ok, we've now decided to do the transformation.
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// If 64-bit shifts are legal, use the extract-shift sequence,
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// otherwise bounce the vector off the cache.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue Vals[4];
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SDLoc dl(InputVector);
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if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
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SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
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EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
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SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
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DAG.getConstant(0, VecIdxTy));
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SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
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DAG.getConstant(1, VecIdxTy));
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// Store the value to a temporary stack slot.
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SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
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SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
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MachinePointerInfo(), false, false, 0);
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SDValue ShAmt = DAG.getConstant(32,
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DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
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Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
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Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
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DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
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Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
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Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
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DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
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} else {
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// Store the value to a temporary stack slot.
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SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
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SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
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MachinePointerInfo(), false, false, 0);
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// Replace each use (extract) with a load of the appropriate element.
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EVT ElementType = InputVector.getValueType().getVectorElementType();
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unsigned EltSize = ElementType.getSizeInBits() / 8;
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// Replace each use (extract) with a load of the appropriate element.
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for (unsigned i = 0; i < 4; ++i) {
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uint64_t Offset = EltSize * i;
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SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
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SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
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StackPtr, OffsetVal);
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// Load the scalar.
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Vals[i] = DAG.getLoad(ElementType, dl, Ch,
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ScalarAddr, MachinePointerInfo(),
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false, false, false, 0);
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}
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}
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// Replace the extracts
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for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
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UE = Uses.end(); UI != UE; ++UI) {
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UE = Uses.end(); UI != UE; ++UI) {
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SDNode *Extract = *UI;
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// cOMpute the element's address.
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SDValue Idx = Extract->getOperand(1);
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unsigned EltSize =
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InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
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uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
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SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
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StackPtr, OffsetVal);
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// Load the scalar.
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SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
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ScalarAddr, MachinePointerInfo(),
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false, false, false, 0);
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// Replace the exact with the load.
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DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
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uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
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}
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// The replacement was made in place; don't return anything.
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@ -1,35 +1,38 @@
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; RUN: llc -mtriple=x86_64-linux -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN
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; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=WIN
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; RUN: llc -mtriple=i686-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN32
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; rdar://7398554
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; When doing vector gather-scatter index calculation with 32-bit indices,
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; bounce the vector off of cache rather than shuffling each individual
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; use an efficient mov/shift sequence rather than shuffling each individual
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; element out of the index vector.
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; CHECK: foo:
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; LIN: movaps (%rsi), %xmm0
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; LIN: andps (%rdx), %xmm0
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; LIN: movaps %xmm0, -24(%rsp)
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; LIN: movslq -24(%rsp), %[[REG1:r.+]]
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; LIN: movslq -20(%rsp), %[[REG2:r.+]]
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; LIN: movslq -16(%rsp), %[[REG3:r.+]]
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; LIN: movslq -12(%rsp), %[[REG4:r.+]]
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; LIN: movsd (%rdi,%[[REG1]],8), %xmm0
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; LIN: movhpd (%rdi,%[[REG2]],8), %xmm0
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; LIN: movsd (%rdi,%[[REG3]],8), %xmm1
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; LIN: movhpd (%rdi,%[[REG4]],8), %xmm1
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; CHECK-LABEL: foo:
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; LIN: movdqa (%rsi), %xmm0
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; LIN: pand (%rdx), %xmm0
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; LIN: pextrq $1, %xmm0, %r[[REG4:.+]]
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; LIN: movd %xmm0, %r[[REG2:.+]]
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; LIN: movslq %e[[REG2]], %r[[REG1:.+]]
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; LIN: sarq $32, %r[[REG2]]
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; LIN: movslq %e[[REG4]], %r[[REG3:.+]]
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; LIN: sarq $32, %r[[REG4]]
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; LIN: movsd (%rdi,%r[[REG1]],8), %xmm0
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; LIN: movhpd (%rdi,%r[[REG2]],8), %xmm0
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; LIN: movsd (%rdi,%r[[REG3]],8), %xmm1
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; LIN: movhpd (%rdi,%r[[REG4]],8), %xmm1
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; WIN: movaps (%rdx), %xmm0
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; WIN: andps (%r8), %xmm0
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; WIN: movaps %xmm0, (%rsp)
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; WIN: movslq (%rsp), %[[REG1:r.+]]
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; WIN: movslq 4(%rsp), %[[REG2:r.+]]
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; WIN: movslq 8(%rsp), %[[REG3:r.+]]
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; WIN: movslq 12(%rsp), %[[REG4:r.+]]
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; WIN: movsd (%rcx,%[[REG1]],8), %xmm0
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; WIN: movhpd (%rcx,%[[REG2]],8), %xmm0
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; WIN: movsd (%rcx,%[[REG3]],8), %xmm1
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; WIN: movhpd (%rcx,%[[REG4]],8), %xmm1
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; WIN: movdqa (%rdx), %xmm0
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; WIN: pand (%r8), %xmm0
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; WIN: pextrq $1, %xmm0, %r[[REG4:.+]]
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; WIN: movd %xmm0, %r[[REG2:.+]]
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; WIN: movslq %e[[REG2]], %r[[REG1:.+]]
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; WIN: sarq $32, %r[[REG2]]
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; WIN: movslq %e[[REG4]], %r[[REG3:.+]]
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; WIN: sarq $32, %r[[REG4]]
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; WIN: movsd (%rcx,%r[[REG1]],8), %xmm0
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; WIN: movhpd (%rcx,%r[[REG2]],8), %xmm0
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; WIN: movsd (%rcx,%r[[REG3]],8), %xmm1
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; WIN: movhpd (%rcx,%r[[REG4]],8), %xmm1
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define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind {
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%a = load <4 x i32>* %i
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@ -53,3 +56,35 @@ define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind {
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%v3 = insertelement <4 x double> %v2, double %r3, i32 3
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ret <4 x double> %v3
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}
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; Check that the sequence previously used above, which bounces the vector off the
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; cache works for x86-32. Note that in this case it will not be used for index
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; calculation, since indexes are 32-bit, not 64.
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; CHECK-LABEL: old:
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; LIN32: movaps %xmm0, (%esp)
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; LIN32-DAG: {{(mov|and)}}l (%esp),
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; LIN32-DAG: {{(mov|and)}}l 4(%esp),
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; LIN32-DAG: {{(mov|and)}}l 8(%esp),
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; LIN32-DAG: {{(mov|and)}}l 12(%esp),
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define <4 x i64> @old(double* %p, <4 x i32>* %i, <4 x i32>* %h, i64 %f) nounwind {
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%a = load <4 x i32>* %i
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%b = load <4 x i32>* %h
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%j = and <4 x i32> %a, %b
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%d0 = extractelement <4 x i32> %j, i32 0
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%d1 = extractelement <4 x i32> %j, i32 1
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%d2 = extractelement <4 x i32> %j, i32 2
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%d3 = extractelement <4 x i32> %j, i32 3
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%q0 = zext i32 %d0 to i64
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%q1 = zext i32 %d1 to i64
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%q2 = zext i32 %d2 to i64
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%q3 = zext i32 %d3 to i64
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%r0 = and i64 %q0, %f
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%r1 = and i64 %q1, %f
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%r2 = and i64 %q2, %f
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%r3 = and i64 %q3, %f
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%v0 = insertelement <4 x i64> undef, i64 %r0, i32 0
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%v1 = insertelement <4 x i64> %v0, i64 %r1, i32 1
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%v2 = insertelement <4 x i64> %v1, i64 %r2, i32 2
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%v3 = insertelement <4 x i64> %v2, i64 %r3, i32 3
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ret <4 x i64> %v3
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}
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