6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-21 23:17:16 +00:00
Code Issues Projects Releases Wiki Activity

Teach the AArch64 backend about v4f16 and v8f16

Browse Source 
This teaches the AArch64 backend to deal with the operations required
to deal with the operations on v4f16 and v8f16 which are exposed by
NEON intrinsics, plus the add, sub, mul and div operations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard
2014-08-27 16:16:04 +00:00
parent b8c95a89e6
commit 5e487f8dc7
15 changed files with 1893 additions and 132 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+17 -6
View File
@@ -370,9 +370,11 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
}
// The rest of the time, vector "promotion" is basically just bitcasting and
// doing the operation in a different type. For example, x86 promotes
// ISD::AND on v2i32 to v1i64.
// There are currently two cases of vector promotion:
// 1) Bitcasting a vector of integers to a different type to a vector of the
// same overall length. For example, x86 promotes ISD::AND on v2i32 to v1i64.
// 2) Extending a vector of floats to a vector of the same number oflarger
// floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
MVT VT = Op.getSimpleValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");
@@ -382,14 +384,23 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
if (Op.getOperand(j).getValueType().isVector())
Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
if (Op.getOperand(j)
.getValueType()
.getVectorElementType()
.isFloatingPoint())
Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
else
Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
else
Operands[j] = Op.getOperand(j);
}
Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
return DAG.getNode(ISD::BITCAST, dl, VT, Op);
if (VT.isFloatingPoint() ||
(VT.isVector() && VT.getVectorElementType().isFloatingPoint()))
return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
else
return DAG.getNode(ISD::BITCAST, dl, VT, Op);
}
SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {