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Rename TargetRegisterDesc to MCRegisterDesc

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-06-24 23:44:48 +00:00
parent ba8297ec08
commit 5e6b4605bd
3 changed files with 4 additions and 7 deletions
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4
include/llvm/MC/MCRegisterInfo.h
View File

@ -20,7 +20,7 @@
namespace llvm { namespace llvm {
/// TargetRegisterDesc - This record contains all of the information known about /// MCRegisterDesc - This record contains all of the information known about
/// a particular register. The Overlaps field contains a pointer to a zero /// a particular register. The Overlaps field contains a pointer to a zero
/// terminated array of registers that this register aliases, starting with /// terminated array of registers that this register aliases, starting with
/// itself. This is needed for architectures like X86 which have AL alias AX /// itself. This is needed for architectures like X86 which have AL alias AX
@ -38,7 +38,7 @@ struct MCRegisterDesc {
}; };
/// MCRegisterInfo base class - We assume that the target defines a static /// MCRegisterInfo base class - We assume that the target defines a static
/// array of TargetRegisterDesc objects that represent all of the machine /// array of MCRegisterDesc objects that represent all of the machine
/// registers that the target has. As such, we simply have to track a pointer /// registers that the target has. As such, we simply have to track a pointer
/// to this array so that we can turn register number into a register /// to this array so that we can turn register number into a register
/// descriptor. /// descriptor.

3
include/llvm/Target/TargetRegisterInfo.h
View File

@ -256,9 +256,6 @@ public:
bool isAllocatable() const { return Allocatable; } bool isAllocatable() const { return Allocatable; }
}; };
/// TargetRegisterDesc - It's just an alias of MCRegisterDesc.
typedef MCRegisterDesc TargetRegisterDesc;
/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
/// registers. These are used by codegen, not by MC. /// registers. These are used by codegen, not by MC.
struct TargetRegisterInfoDesc { struct TargetRegisterInfoDesc {

4
utils/TableGen/RegisterInfoEmitter.cpp
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@ -79,7 +79,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
<< " explicit " << ClassName << " explicit " << ClassName
<< "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, " << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
<< "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, " << " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n" << "unsigned Flavour) const;\n"
@ -518,7 +518,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// Emit the constructor of the class... // Emit the constructor of the class...
OS << ClassName << "::" << ClassName OS << ClassName << "::" << ClassName
<< "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, " << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
<< "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(ID" << " : TargetRegisterInfo(ID"
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"