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Constify some methods. Patch provided by Anton Vayvod, thanks!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-08-17 22:00:08 +00:00
parent c0431fe1ca
commit 5ea64fd9eb
11 changed files with 42 additions and 37 deletions
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5
include/llvm/CodeGen/MachineFunction.h
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@@ -165,6 +165,11 @@ public:
return static_cast<Ty*>(MFInfo); return static_cast<Ty*>(MFInfo);
} }
template<typename Ty>
const Ty *getInfo() const {
return const_cast<MachineFunction*>(this)->getInfo<Ty>();
}
/// setUsedPhysRegs - The register allocator should call this to initialized /// setUsedPhysRegs - The register allocator should call this to initialized
/// the UsedPhysRegs set. This should be passed a new[]'d array with entries /// the UsedPhysRegs set. This should be passed a new[]'d array with entries
/// for all of the physical registers that the target supports. Each array /// for all of the physical registers that the target supports. Each array

4
include/llvm/Target/MRegisterInfo.h
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@@ -170,10 +170,10 @@ public:
/// ///
/// By default, these methods return all registers in the class. /// By default, these methods return all registers in the class.
/// ///
virtual iterator allocation_order_begin(MachineFunction &MF) const { virtual iterator allocation_order_begin(const MachineFunction &MF) const {
return begin(); return begin();
} }
virtual iterator allocation_order_end(MachineFunction &MF) const { virtual iterator allocation_order_end(const MachineFunction &MF) const {
return end(); return end();
} }

4
lib/Target/ARM/ARMRegisterInfo.td
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@@ -45,11 +45,11 @@ def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
R7, R8, R9, R10, R11, R12, R7, R8, R9, R10, R11, R12,
R13, R14, R15]> { R13, R14, R15]> {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
IntRegsClass::iterator IntRegsClass::iterator
IntRegsClass::allocation_order_end(MachineFunction &MF) const { IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
// r15 == Program Counter // r15 == Program Counter
// r14 == Link Register // r14 == Link Register
// r13 == Stack Pointer // r13 == Stack Pointer

2
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@@ -180,7 +180,7 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const {
// pointer register. This is true if the function has variable sized allocas or // pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled. // if frame pointer elimination is disabled.
// //
static bool hasFP(MachineFunction &MF) { static bool hasFP(const MachineFunction &MF) {
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->hasVarSizedObjects(); return MFI->hasVarSizedObjects();
} }

12
lib/Target/Alpha/AlphaRegisterInfo.td
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@@ -124,11 +124,11 @@ def GPRC : RegisterClass<"Alpha", [i64], 64,
R15, R30, R31 ]> //zero R15, R30, R31 ]> //zero
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
GPRCClass::iterator GPRCClass::iterator
GPRCClass::allocation_order_end(MachineFunction &MF) const { GPRCClass::allocation_order_end(const MachineFunction &MF) const {
return end()-3; return end()-3;
} }
}]; }];
@@ -142,11 +142,11 @@ def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1,
F31 ]> //zero F31 ]> //zero
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
F4RCClass::iterator F4RCClass::iterator
F4RCClass::allocation_order_end(MachineFunction &MF) const { F4RCClass::allocation_order_end(const MachineFunction &MF) const {
return end()-1; return end()-1;
} }
}]; }];
@@ -160,11 +160,11 @@ def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1,
F31 ]> //zero F31 ]> //zero
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
F8RCClass::iterator F8RCClass::iterator
F8RCClass::allocation_order_end(MachineFunction &MF) const { F8RCClass::allocation_order_end(const MachineFunction &MF) const {
return end()-1; return end()-1;
} }
}]; }];

2
lib/Target/IA64/IA64RegisterInfo.cpp
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@@ -113,7 +113,7 @@ IA64RegisterInfo::getCalleeSaveRegClasses() const {
// pointer register. This is true if the function has variable sized allocas or // pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled. // if frame pointer elimination is disabled.
// //
static bool hasFP(MachineFunction &MF) { static bool hasFP(const MachineFunction &MF) {
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
} }

16
lib/Target/IA64/IA64RegisterInfo.td
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@@ -422,18 +422,18 @@ def GR : RegisterClass<"IA64", [i64], 64,
r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down) r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down)
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_begin(MachineFunction &MF) const; iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
GRClass::iterator GRClass::iterator
GRClass::allocation_order_begin(MachineFunction &MF) const { GRClass::allocation_order_begin(const MachineFunction &MF) const {
// hide the 8 out? registers appropriately: // hide the 8 out? registers appropriately:
return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed)); return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
} }
GRClass::iterator GRClass::iterator
GRClass::allocation_order_end(MachineFunction &MF) const { GRClass::allocation_order_end(const MachineFunction &MF) const {
int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc
// we also can't allocate registers for use as locals if they're // we also can't allocate registers for use as locals if they're
@@ -472,17 +472,17 @@ def FP : RegisterClass<"IA64", [f64], 64,
let Alignment=128; let Alignment=128;
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_begin(MachineFunction &MF) const; iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
FPClass::iterator FPClass::iterator
FPClass::allocation_order_begin(MachineFunction &MF) const { FPClass::allocation_order_begin(const MachineFunction &MF) const {
return begin(); // we don't hide any FP regs from the start return begin(); // we don't hide any FP regs from the start
} }
FPClass::iterator FPClass::iterator
FPClass::allocation_order_end(MachineFunction &MF) const { FPClass::allocation_order_end(const MachineFunction &MF) const {
return end()-2; // we hide regs F0, F1 from the end return end()-2; // we hide regs F0, F1 from the end
} }
}]; }];

16
lib/Target/PowerPC/PPCRegisterInfo.td
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@@ -209,16 +209,16 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
R16, R15, R14, R13, R31, R0, R1, LR]> R16, R15, R14, R13, R31, R0, R1, LR]>
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_begin(MachineFunction &MF) const; iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
GPRCClass::iterator GPRCClass::iterator
GPRCClass::allocation_order_begin(MachineFunction &MF) const { GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
return begin(); return begin();
} }
GPRCClass::iterator GPRCClass::iterator
GPRCClass::allocation_order_end(MachineFunction &MF) const { GPRCClass::allocation_order_end(const MachineFunction &MF) const {
if (hasFP(MF)) if (hasFP(MF))
return end()-4; // don't allocate R31, R0, R1, LR return end()-4; // don't allocate R31, R0, R1, LR
else else
@@ -232,16 +232,16 @@ def G8RC : RegisterClass<"PPC", [i64], 64,
X16, X15, X14, X13, X31, X0, X1]> X16, X15, X14, X13, X31, X0, X1]>
{ {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_begin(MachineFunction &MF) const; iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
G8RCClass::iterator G8RCClass::iterator
G8RCClass::allocation_order_begin(MachineFunction &MF) const { G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
return begin(); return begin();
} }
G8RCClass::iterator G8RCClass::iterator
G8RCClass::allocation_order_end(MachineFunction &MF) const { G8RCClass::allocation_order_end(const MachineFunction &MF) const {
if (hasFP(MF)) if (hasFP(MF))
return end()-3; return end()-3;
else else

4
lib/Target/Sparc/SparcRegisterInfo.td
View File

@@ -138,11 +138,11 @@ def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
G5, G6, G7 // reserved for kernel G5, G6, G7 // reserved for kernel
]> { ]> {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
IntRegsClass::iterator IntRegsClass::iterator
IntRegsClass::allocation_order_end(MachineFunction &MF) const { IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
// FIXME: These special regs should be taken out of the regclass! // FIXME: These special regs should be taken out of the regclass!
return end()-10 // Don't allocate special registers return end()-10 // Don't allocate special registers
-1; // FIXME: G1 reserved for large imm generation by frame code. -1; // FIXME: G1 reserved for large imm generation by frame code.

2
lib/Target/X86/X86RegisterInfo.cpp
View File

@@ -737,7 +737,7 @@ X86RegisterInfo::getCalleeSaveRegClasses() const {
// pointer register. This is true if the function has variable sized allocas or // pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled. // if frame pointer elimination is disabled.
// //
static bool hasFP(MachineFunction &MF) { static bool hasFP(const MachineFunction &MF) {
return (NoFramePointerElim || return (NoFramePointerElim ||
MF.getFrameInfo()->hasVarSizedObjects() || MF.getFrameInfo()->hasVarSizedObjects() ||
MF.getInfo<X86FunctionInfo>()->getForceFramePointer()); MF.getInfo<X86FunctionInfo>()->getForceFramePointer());

12
lib/Target/X86/X86RegisterInfo.td
View File

@@ -107,11 +107,11 @@ def GR8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
GR16Class::iterator GR16Class::iterator
GR16Class::allocation_order_end(MachineFunction &MF) const { GR16Class::allocation_order_end(const MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
return end()-2; // If so, don't allocate SP or BP return end()-2; // If so, don't allocate SP or BP
else else
@@ -123,11 +123,11 @@ def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
def GR32 : RegisterClass<"X86", [i32], 32, def GR32 : RegisterClass<"X86", [i32], 32,
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> { [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
GR32Class::iterator GR32Class::iterator
GR32Class::allocation_order_end(MachineFunction &MF) const { GR32Class::allocation_order_end(const MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
return end()-2; // If so, don't allocate ESP or EBP return end()-2; // If so, don't allocate ESP or EBP
else else
@@ -160,11 +160,11 @@ def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
def RST : RegisterClass<"X86", [f64], 32, def RST : RegisterClass<"X86", [f64], 32,
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
let MethodProtos = [{ let MethodProtos = [{
iterator allocation_order_end(MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const;
}]; }];
let MethodBodies = [{ let MethodBodies = [{
RSTClass::iterator RSTClass::iterator
RSTClass::allocation_order_end(MachineFunction &MF) const { RSTClass::allocation_order_end(const MachineFunction &MF) const {
return begin(); return begin();
} }
}]; }];