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Allow CONCAT_VECTORS nodes to be legal or have custom lowering for some targets.
Changes to take advantage of this will come later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70560 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1750,23 +1750,46 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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break;
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case ISD::CONCAT_VECTORS: {
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case ISD::CONCAT_VECTORS: {
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// Use extract/insert/build vector for now. We might try to be
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// Legalize the operands.
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// more clever later.
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MVT PtrVT = TLI.getPointerTy();
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SmallVector<SDValue, 8> Ops;
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SmallVector<SDValue, 8> Ops;
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unsigned NumOperands = Node->getNumOperands();
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
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for (unsigned i=0; i < NumOperands; ++i) {
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Ops.push_back(LegalizeOp(Node->getOperand(i)));
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SDValue SubOp = Node->getOperand(i);
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Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
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MVT VVT = SubOp.getNode()->getValueType(0);
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MVT EltVT = VVT.getVectorElementType();
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switch (TLI.getOperationAction(ISD::CONCAT_VECTORS,
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unsigned NumSubElem = VVT.getVectorNumElements();
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Node->getValueType(0))) {
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for (unsigned j=0; j < NumSubElem; ++j) {
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default: assert(0 && "Unknown operation action!");
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
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case TargetLowering::Legal:
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DAG.getConstant(j, PtrVT)));
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break;
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case TargetLowering::Custom:
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Tmp3 = TLI.LowerOperation(Result, DAG);
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if (Tmp3.getNode()) {
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Result = Tmp3;
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break;
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}
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}
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// FALLTHROUGH
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case TargetLowering::Expand: {
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// Use extract/insert/build vector for now. We might try to be
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// more clever later.
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MVT PtrVT = TLI.getPointerTy();
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SmallVector<SDValue, 8> Ops;
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unsigned NumOperands = Node->getNumOperands();
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for (unsigned i=0; i < NumOperands; ++i) {
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SDValue SubOp = Node->getOperand(i);
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MVT VVT = SubOp.getNode()->getValueType(0);
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MVT EltVT = VVT.getVectorElementType();
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unsigned NumSubElem = VVT.getVectorNumElements();
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for (unsigned j=0; j < NumSubElem; ++j) {
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
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DAG.getConstant(j, PtrVT)));
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}
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}
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return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl,
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Node->getValueType(0),
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&Ops[0], Ops.size()));
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}
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}
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return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
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}
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&Ops[0], Ops.size()));
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break;
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}
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}
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case ISD::CALLSEQ_START: {
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case ISD::CALLSEQ_START: {
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@ -443,6 +443,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
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// These operations default to expand.
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// These operations default to expand.
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setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
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}
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}
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// Most targets ignore the @llvm.prefetch intrinsic.
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// Most targets ignore the @llvm.prefetch intrinsic.
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