6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-14 17:34:41 +00:00
Code Issues Projects Releases Wiki Activity

Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap

Browse Source 
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2008-08-22 03:49:10 +00:00
parent 0bfb75277f
commit 5f0cfa299d
3 changed files with 19 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -4056,20 +4056,20 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// loopMBB:
// l[wd]arx dest, ptr
// cmp[wd] dest, oldval
// bne- exitMBB
// cmp[wd] CR1, dest, oldval
// st[wd]cx. newval, ptr
// bne- CR1, exitMBB
// bne- loopMBB
// fallthrough --> exitMBB
BB = loopMBB;
BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
.addReg(ptrA).addReg(ptrB);
BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR1)
.addReg(oldval).addReg(dest);
BuildMI(BB, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(exitMBB);
BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(newval).addReg(ptrA).addReg(ptrB);
BuildMI(BB, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR1).addMBB(exitMBB);
BuildMI(BB, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);

11
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -123,15 +123,18 @@ let usesCustomDAGSchedInserter = 1 in {
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
"${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
[(set G8RC:$dst, (PPCatomic_load_add xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_CMP_SWAP_I64 : Pseudo<
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
"${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
[(set G8RC:$dst, (PPCatomic_cmp_swap xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
def ATOMIC_SWAP_I64 : Pseudo<
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
"${:comment} ATOMIC_SWAP_I64 PSEUDO!",
[(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>;
}
let Uses = [CR0, CR1] in {
def ATOMIC_CMP_SWAP_I64 : Pseudo<
(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
"${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
[(set G8RC:$dst,
(PPCatomic_cmp_swap xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
}
}
// Instructions to support atomic operations

11
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -553,15 +553,18 @@ let usesCustomDAGSchedInserter = 1 in {
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
"${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
[(set GPRC:$dst, (PPCatomic_load_add xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_CMP_SWAP_I32 : Pseudo<
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
[(set GPRC:$dst, (PPCatomic_cmp_swap xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
def ATOMIC_SWAP_I32 : Pseudo<
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
"${:comment} ATOMIC_SWAP_I32 PSEUDO!",
[(set GPRC:$dst, (PPCatomic_swap xoaddr:$ptr, GPRC:$new))]>;
}
let Uses = [CR0, CR1] in {
def ATOMIC_CMP_SWAP_I32 : Pseudo<
(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
[(set GPRC:$dst,
(PPCatomic_cmp_swap xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
}
}
// Instructions to support atomic operations