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ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
558b66d3cd
commit
5f16057d1e
@ -79,6 +79,8 @@ class ARMAsmParser : public TargetAsmParser {
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out);
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StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
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bool &CarrySetting, unsigned &ProcessorIMod);
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void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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bool &CanAcceptPredicationCode);
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@ -1952,10 +1954,10 @@ ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
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/// setting letters to form a canonical mnemonic and flags.
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//
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// FIXME: Would be nice to autogen this.
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static StringRef SplitMnemonic(StringRef Mnemonic,
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unsigned &PredicationCode,
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bool &CarrySetting,
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unsigned &ProcessorIMod) {
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StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
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unsigned &PredicationCode,
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bool &CarrySetting,
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unsigned &ProcessorIMod) {
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PredicationCode = ARMCC::AL;
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CarrySetting = false;
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ProcessorIMod = 0;
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@ -1963,19 +1965,19 @@ static StringRef SplitMnemonic(StringRef Mnemonic,
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// Ignore some mnemonics we know aren't predicated forms.
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//
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// FIXME: Would be nice to autogen this.
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if (Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "movs" ||
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Mnemonic == "svc" || Mnemonic == "mls" || Mnemonic == "smmls" ||
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Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vnmls" ||
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Mnemonic == "vacge" || Mnemonic == "vcge" || Mnemonic == "vclt" ||
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Mnemonic == "vacgt" || Mnemonic == "vcgt" || Mnemonic == "vcle" ||
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Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
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Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
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Mnemonic == "vqdmlal")
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if ((Mnemonic == "movs" && isThumb()) ||
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Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
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Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
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Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
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Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
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Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
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Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
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Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
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return Mnemonic;
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// First, split out any predication code. Ignore mnemonics we know aren't
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// predicated but do have a carry-set and so weren't caught above.
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if (Mnemonic != "adcs" && Mnemonic != "bics") {
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if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") {
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unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
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.Case("eq", ARMCC::EQ)
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.Case("ne", ARMCC::NE)
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@ -2005,10 +2007,10 @@ static StringRef SplitMnemonic(StringRef Mnemonic,
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// the instructions we know end in 's'.
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if (Mnemonic.endswith("s") &&
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!(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
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Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
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Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
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Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
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Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
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Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
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Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
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Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
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Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) {
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Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
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CarrySetting = true;
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}
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@ -2056,8 +2058,8 @@ GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
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Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
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Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
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Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
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Mnemonic == "clrex" || Mnemonic.startswith("cps")) {
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Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
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Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
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CanAcceptPredicationCode = false;
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} else {
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CanAcceptPredicationCode = true;
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@ -678,12 +678,31 @@ _func:
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mov r5, #0xff0000
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mov r6, #0xffff
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movw r9, #0xffff
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movs r3, #7
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moveq r4, #0xff0
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movseq r5, #0xff0000
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@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3]
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@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3]
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@ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3]
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@ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3]
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@ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3]
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@ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3]
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@ CHECK: moveq r4, #4080 @ encoding: [0xff,0x4e,0xa0,0x03]
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@ CHECK: movseq r5, #16711680 @ encoding: [0xff,0x58,0xb0,0x03]
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@------------------------------------------------------------------------------
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@ MOV (register)
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@------------------------------------------------------------------------------
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mov r2, r3
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movs r2, r3
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moveq r2, r3
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movseq r2, r3
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@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1]
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@ CHECK: movs r2, r3 @ encoding: [0x03,0x20,0xb0,0xe1]
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@ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01]
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@ CHECK: movseq r2, r3 @ encoding: [0x03,0x20,0xb0,0x01]
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@------------------------------------------------------------------------------
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@ STM*
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@ -93,3 +93,9 @@
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@ Out of range immediate for MOV
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movw r9, 0x10000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Invalid 's' bit usage for MOVW
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movs r6, #0xffff
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movwseq r9, #0xffff
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified
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