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https://github.com/c64scene-ar/llvm-6502.git
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Rewrite address mode 1 code emission routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56171 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
0b23ac1fcf
commit
5f1db7bf31
@ -57,7 +57,12 @@ namespace {
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private:
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unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &Desc,
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unsigned Binary) ;
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unsigned Binary);
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unsigned getMachineSoRegOpValue(const MachineInstr &MI,
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const TargetInstrDesc &Desc,
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unsigned OpIdx);
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unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &Desc,
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unsigned Binary);
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@ -259,145 +264,114 @@ unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
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return Binary;
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}
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unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
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const TargetInstrDesc &Desc,
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unsigned OpIdx) {
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// Set last operand (register Rm)
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unsigned Binary = getMachineOpValue(MI, OpIdx);
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const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
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const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
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ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
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// Encode the shift opcode.
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unsigned SBits = 0;
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unsigned Rs = MO1.getReg();
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if (Rs) {
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// Set shift operand (bit[7:4]).
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// LSL - 0001
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// LSR - 0011
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// ASR - 0101
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// ROR - 0111
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// RRX - 0110 and bit[11:8] clear.
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switch (SOpc) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::lsl: SBits = 0x1; break;
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case ARM_AM::lsr: SBits = 0x3; break;
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case ARM_AM::asr: SBits = 0x5; break;
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case ARM_AM::ror: SBits = 0x7; break;
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case ARM_AM::rrx: SBits = 0x6; break;
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}
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} else {
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// Set shift operand (bit[6:4]).
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// LSL - 000
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// LSR - 010
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// ASR - 100
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// ROR - 110
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switch (SOpc) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::lsl: SBits = 0x0; break;
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case ARM_AM::lsr: SBits = 0x2; break;
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case ARM_AM::asr: SBits = 0x4; break;
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case ARM_AM::ror: SBits = 0x6; break;
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}
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}
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Binary |= SBits << 4;
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if (SOpc == ARM_AM::rrx)
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return Binary;
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// Encode the shift operation Rs or shift_imm (except rrx).
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if (Rs) {
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// Encode Rs bit[11:8].
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assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
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return Binary |
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(ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
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}
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// Encode shift_imm bit[11:7].
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return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
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}
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unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &Desc,
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unsigned Binary) {
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// FIXME: Clean up.
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// Treat 3 special instructions: MOVsra_flag, MOVsrl_flag and MOVrx.
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if (MI.getOpcode() == ARM::MOVi2pieces)
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// FIXME.
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abort();
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unsigned Format = Desc.TSFlags & ARMII::FormMask;
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if (Format == ARMII::DPRdMisc) {
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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Binary |= getMachineOpValue(MI, 1);
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switch (Desc.Opcode) {
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case ARM::MOVsra_flag:
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Binary |= 0x1 << 6;
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Binary |= 0x1 << 7;
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break;
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case ARM::MOVsrl_flag:
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Binary |= 0x1 << 5;
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Binary |= 0x1 << 7;
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break;
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case ARM::MOVrx:
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Binary |= 0x3 << 5;
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break;
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}
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return Binary;
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// FIXME: Consolidate into a single bit.
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bool isUnary = (Format == ARMII::DPRdMisc ||
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Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg ||
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Format == ARMII::DPRnIm ||
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Format == ARMII::DPRnReg ||
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Format == ARMII::DPRnSoReg);
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unsigned OpIdx = 0;
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// Encode register def if there is one.
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unsigned NumDefs = Desc.getNumDefs();
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if (NumDefs) {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
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++OpIdx;
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}
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// FIXME: Clean up this part.
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// Data processing operand instructions has 3 possible encodings (for more
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// information, see ARM-ARM page A3-10):
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// 1. <instr> <Rd>,<shifter_operand>
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// 2. <instr> <Rn>,<shifter_operand>
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// 3. <instr> <Rd>,<Rn>,<shifter_operand>
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bool IsDataProcessing1 = Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg;
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bool IsDataProcessing2 = Format == ARMII::DPRnIm ||
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Format == ARMII::DPRnReg ||
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Format == ARMII::DPRnSoReg;
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bool IsDataProcessing3 = false;
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if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS ||
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Format == ARMII::DPRSoRegS || IsDataProcessing2)
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IsDataProcessing3 = !IsDataProcessing2;
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IsDataProcessing3 = Format == ARMII::DPRIm ||
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Format == ARMII::DPRReg ||
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Format == ARMII::DPRSoReg ||
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IsDataProcessing3;
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// Set first operand
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if (IsDataProcessing1 || IsDataProcessing3) {
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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} else if (IsDataProcessing2) {
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
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// Encode first non-shifter register operand if ther is one.
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if (!isUnary) {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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// Set second operand of data processing #3 instructions
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if (IsDataProcessing3)
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Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
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// Encode shifter operand.
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if (Desc.getNumOperands() - OpIdx > 1)
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// Encode SoReg.
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return Binary | getMachineSoRegOpValue(MI, Desc, OpIdx);
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unsigned OpIdx = IsDataProcessing3 ? 2 : 1;
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switch (Format) {
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default:
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assert(false && "Unknown operand type!");
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break;
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case ARMII::DPRdIm: case ARMII::DPRnIm:
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case ARMII::DPRIm: case ARMII::DPRImS: {
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// Set bit I(25) to identify this is the immediate form of <shifter_op>
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Binary |= 1 << ARMII::I_BitShift;
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// Set immed_8 field
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const MachineOperand &MO = MI.getOperand(OpIdx);
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Binary |= ARM_AM::getSOImmVal(MO.getImm());
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break;
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}
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case ARMII::DPRdReg: case ARMII::DPRnReg:
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case ARMII::DPRReg: case ARMII::DPRRegS: {
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// Set last operand (register Rm)
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Binary |= getMachineOpValue(MI, OpIdx);
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break;
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}
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case ARMII::DPRdSoReg: case ARMII::DPRnSoReg:
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case ARMII::DPRSoReg: case ARMII::DPRSoRegS: {
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// Set last operand (register Rm)
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Binary |= getMachineOpValue(MI, OpIdx);
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const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
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const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
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// Identify it the instr is in immed or register shifts encoding
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bool IsShiftByRegister = MO1.getReg() > 0;
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// Set shift operand (bit[6:4]).
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// ASR - 101 if it is in register shifts encoding; 100, otherwise.
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// LSL - 001 if it is in register shifts encoding; 000, otherwise.
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// LSR - 011 if it is in register shifts encoding; 010, otherwise.
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// ROR - 111 if it is in register shifts encoding; 110, otherwise.
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// RRX - 110 and bit[11:7] clear.
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switch (ARM_AM::getSORegShOp(MO2.getImm())) {
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default: assert(0 && "Unknown shift opc!");
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case ARM_AM::asr:
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if (IsShiftByRegister)
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Binary |= 0x5 << 4;
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else
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Binary |= 0x1 << 6;
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break;
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case ARM_AM::lsl:
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if (IsShiftByRegister)
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Binary |= 0x1 << 4;
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break;
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case ARM_AM::lsr:
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if (IsShiftByRegister)
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Binary |= 0x3 << 4;
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else
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Binary |= 0x1 << 5;
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break;
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case ARM_AM::ror:
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if (IsShiftByRegister)
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Binary |= 0x7 << 4;
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else
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Binary |= 0x3 << 5;
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break;
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case ARM_AM::rrx:
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Binary |= 0x3 << 5;
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break;
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}
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// Set the field related to shift operations (except rrx).
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if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
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if (IsShiftByRegister) {
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// Set the value of bit[11:8] (register Rs).
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assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
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Binary |= (ARMRegisterInfo::getRegisterNumbering(MO1.getReg()) <<
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ARMII::RegRsShift);
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} else
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// Set the value of bit [11:7] (shift_immed field).
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Binary |= ARM_AM::getSORegOffset(MO2.getImm()) << 7;
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}
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break;
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}
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}
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const MachineOperand &MO = MI.getOperand(OpIdx);
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if (MO.isRegister())
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// Encode register Rm.
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return Binary | getMachineOpValue(MI, NumDefs + 1);
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// Encode so_imm.
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// Set bit I(25) to identify this is the immediate form of <shifter_op>
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Binary |= 1 << ARMII::I_BitShift;
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unsigned SoImm = MO.getImm();
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// Encode rotate_imm.
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Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
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// Encode immed_8.
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Binary |= ARM_AM::getSOImmVal(SoImm);
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return Binary;
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}
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@ -114,6 +114,7 @@ namespace ARMII {
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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RotImmShift = 8,
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RegRsShift = 8,
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RegRdShift = 12,
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RegRnShift = 16,
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