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(1) Added special register class containing (for now) %fsr.

Browse Source 
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
2003-05-27 00:05:23 +00:00
parent 49cab03c81
commit 5f2180c533
12 changed files with 83 additions and 80 deletions
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2
lib/CodeGen/LiveVariables.cpp
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@ -231,7 +231,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.opIsDef() || MO.opIsDefAndUse()) {
if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
if (MO.isVirtualRegister()) {
VarInfo &VRInfo = getVarInfo(MO.getReg());