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(1) Added special register class containing (for now) %fsr.

Browse Source 
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
2003-05-27 00:05:23 +00:00
parent 49cab03c81
commit 5f2180c533
12 changed files with 83 additions and 80 deletions
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7
lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
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@@ -170,7 +170,7 @@ void LiveRangeInfo::constructLiveRanges() {
// for each operand that is defined by the instruction
for (MachineInstr::val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI)
if (OpI.isDef()) {
if (OpI.isDefOnly() || OpI.isDefAndUse()) {
const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
@@ -180,7 +180,8 @@ void LiveRangeInfo::constructLiveRanges() {
// iterate over implicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
if (MInst->implicitRefIsDefined(i)) {
if (MInst->getImplicitOp(i).opIsDefOnly() ||
MInst->getImplicitOp(i).opIsDefAndUse()) {
const Value *Def = MInst->getImplicitRef(i);
createOrAddToLiveRange(Def, /*isCC*/ false);
}
@@ -264,7 +265,7 @@ void LiveRangeInfo::coalesceLRs()
// iterate over MI operands to find defs
for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
DefE = MI->end(); DefI != DefE; ++DefI) {
if (DefI.isDef()) { // iff this operand is a def
if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified
LiveRange *LROfDef = getLiveRangeForValue( *DefI );
RegClass *RCOfDef = LROfDef->getRegClass();