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Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -15,6 +15,7 @@
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//===----------------------------------------------------------------------===//
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#include "AllocationOrder.h"
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#include "RegisterClassInfo.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -23,8 +24,8 @@ using namespace llvm;
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// Compare VirtRegMap::getRegAllocPref().
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AllocationOrder::AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const BitVector &ReservedRegs)
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: Pos(0), Reserved(ReservedRegs) {
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const RegisterClassInfo &RegClassInfo)
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: Pos(0), RCI(RegClassInfo) {
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const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
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std::pair<unsigned, unsigned> HintPair =
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VRM.getRegInfo().getRegAllocationHint(VirtReg);
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@ -47,7 +48,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
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// The hint must be a valid physreg for allocation.
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if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
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!RC->contains(Hint) || ReservedRegs.test(Hint)))
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!RC->contains(Hint) || RCI.isReserved(Hint)))
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Hint = 0;
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}
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@ -61,7 +62,7 @@ unsigned AllocationOrder::next() {
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// Then look at the order from TRI.
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while(Pos != End) {
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unsigned Reg = *Pos++;
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if (Reg != Hint && !Reserved.test(Reg))
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if (Reg != Hint && !RCI.isReserved(Reg))
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return Reg;
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}
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return 0;
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@ -19,14 +19,14 @@
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namespace llvm {
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class BitVector;
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class RegisterClassInfo;
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class VirtRegMap;
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class AllocationOrder {
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const unsigned *Begin;
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const unsigned *End;
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const unsigned *Pos;
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const BitVector &Reserved;
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const RegisterClassInfo &RCI;
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unsigned Hint;
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public:
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@ -37,7 +37,7 @@ public:
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/// TargetRegisterInfo::getReservedRegs().
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AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const BitVector &ReservedRegs);
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const RegisterClassInfo &RegClassInfo);
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/// next - Return the next physical register in the allocation order, or 0.
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/// It is safe to call next again after it returned 0.
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@ -39,6 +39,7 @@
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#include "llvm/ADT/OwningPtr.h"
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#include "LiveIntervalUnion.h"
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#include "RegisterClassInfo.h"
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namespace llvm {
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@ -91,6 +92,7 @@ protected:
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MachineRegisterInfo *MRI;
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VirtRegMap *VRM;
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LiveIntervals *LIS;
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RegisterClassInfo RegClassInfo;
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LiveUnionArray PhysReg2LiveUnion;
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// Current queries, one per physreg. They must be reinitialized each time we
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@ -13,10 +13,10 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "RegAllocBase.h"
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#include "LiveDebugVariables.h"
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#include "LiveIntervalUnion.h"
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#include "LiveRangeEdit.h"
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#include "RegAllocBase.h"
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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@ -85,7 +85,6 @@ class RABasic : public MachineFunctionPass, public RegAllocBase
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{
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// context
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MachineFunction *MF;
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BitVector ReservedRegs;
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// analyses
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LiveStacks *LS;
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@ -235,6 +234,8 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
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MRI = &vrm.getRegInfo();
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VRM = &vrm;
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LIS = &lis;
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RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
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const unsigned NumRegs = TRI->getNumRegs();
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if (NumRegs != PhysReg2LiveUnion.numRegs()) {
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PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
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@ -479,14 +480,11 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
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SmallVector<unsigned, 8> PhysRegSpillCands;
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// Check for an available register in this class.
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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E = TRC->allocation_order_end(*MF);
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I != E; ++I) {
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ArrayRef<unsigned> Order =
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RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
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for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
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++I) {
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unsigned PhysReg = *I;
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if (ReservedRegs.test(PhysReg)) continue;
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// Check interference and as a side effect, intialize queries for this
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// VirtReg and its aliases.
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@ -537,9 +535,6 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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ReservedRegs = TRI->getReservedRegs(*MF);
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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allocatePhysRegs();
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@ -62,7 +62,6 @@ class RAGreedy : public MachineFunctionPass,
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// context
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MachineFunction *MF;
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BitVector ReservedRegs;
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// analyses
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SlotIndexes *Indexes;
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@ -1410,7 +1409,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
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unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &NewVRegs) {
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// First try assigning a free register.
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AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
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AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
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if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
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return PhysReg;
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@ -1472,7 +1471,6 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
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Indexes = &getAnalysis<SlotIndexes>();
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DomTree = &getAnalysis<MachineDominatorTree>();
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ReservedRegs = TRI->getReservedRegs(*MF);
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SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
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Loops = &getAnalysis<MachineLoopInfo>();
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LoopRanges = &getAnalysis<MachineLoopRanges>();
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@ -12,7 +12,7 @@
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define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
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; CHECK: _ZNKSs7compareERKSs:
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; CHECK: it eq
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; CHECK-NEXT: subeq r0, r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NEXT: ldmia.w sp!,
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entry:
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%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
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