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Add FPExt option to CCValAssign::LocInfo. When generating calling-convention
promotion code, Tablegen will now select FPExt for floating point promotions (previously it had returned AExt, which is not valid for floating point types). Any out-of-tree targets that were relying on AExt being returned for FP promotions will need to update their code check for FPExt instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199252 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,6 +39,7 @@ public:
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VExt, // The value is vector-widened in the location.
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// FIXME: Not implemented yet. Code that uses AExt to mean
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// vector-widen should be fixed to use VExt instead.
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FPExt, // The floating-point value is fp-extended in the location.
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Indirect // The location contains pointer to the value.
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// TODO: a subset of the value is in the location.
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};
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@ -1220,7 +1220,8 @@ AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
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break;
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case CCValAssign::SExt:
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case CCValAssign::ZExt:
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case CCValAssign::AExt: {
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case CCValAssign::AExt:
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case CCValAssign::FPExt: {
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unsigned DestSize = VA.getValVT().getSizeInBits();
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unsigned DestSubReg;
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@ -1441,7 +1442,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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case CCValAssign::ZExt:
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case CCValAssign::AExt: {
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case CCValAssign::AExt:
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case CCValAssign::FPExt: {
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unsigned SrcSize = VA.getValVT().getSizeInBits();
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unsigned SrcSubReg;
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@ -271,6 +271,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
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// Integer return values must be sign or zero extended by the callee.
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switch (VA.getLocInfo()) {
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
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break;
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@ -279,8 +280,9 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
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break;
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case CCValAssign::AExt:
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OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
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default:
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break;
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default:
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llvm_unreachable("Unknown loc info!");
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}
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// The custom bit on an i32 return value indicates that it should be passed
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@ -2111,6 +2111,8 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
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// FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
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// support this.
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return false;
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case CCValAssign::FPExt:
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llvm_unreachable("Unexpected loc info!");
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}
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if (VA.isRegLoc()) {
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@ -1840,6 +1840,9 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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else if (VA.getLocInfo() == CCValAssign::BCvt)
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ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
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assert(VA.getLocInfo() != CCValAssign::FPExt &&
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"Unexpected FP-extend for return value.");
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// If this is x86-64, and we disabled SSE, we can't return FP values,
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// or SSE or MMX vectors.
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if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
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@ -193,13 +193,18 @@ void CallingConvEmitter::EmitAction(Record *Action,
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O << IndentStr << "return false;\n";
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} else if (Action->isSubClassOf("CCPromoteToType")) {
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Record *DestTy = Action->getValueAsDef("DestTy");
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O << IndentStr << "LocVT = " << getEnumName(getValueType(DestTy)) <<";\n";
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O << IndentStr << "if (ArgFlags.isSExt())\n"
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<< IndentStr << IndentStr << "LocInfo = CCValAssign::SExt;\n"
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<< IndentStr << "else if (ArgFlags.isZExt())\n"
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<< IndentStr << IndentStr << "LocInfo = CCValAssign::ZExt;\n"
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<< IndentStr << "else\n"
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<< IndentStr << IndentStr << "LocInfo = CCValAssign::AExt;\n";
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MVT::SimpleValueType DestVT = getValueType(DestTy);
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O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n";
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if (MVT(DestVT).isFloatingPoint()) {
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O << IndentStr << "LocInfo = CCValAssign::FPExt;\n";
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} else {
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O << IndentStr << "if (ArgFlags.isSExt())\n"
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<< IndentStr << IndentStr << "LocInfo = CCValAssign::SExt;\n"
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<< IndentStr << "else if (ArgFlags.isZExt())\n"
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<< IndentStr << IndentStr << "LocInfo = CCValAssign::ZExt;\n"
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<< IndentStr << "else\n"
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<< IndentStr << IndentStr << "LocInfo = CCValAssign::AExt;\n";
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}
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} else if (Action->isSubClassOf("CCBitConvertToType")) {
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Record *DestTy = Action->getValueAsDef("DestTy");
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O << IndentStr << "LocVT = " << getEnumName(getValueType(DestTy)) <<";\n";
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